/*
 * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
 * 
 * SPDX-License-Identifier: Apache-2.0
 * 
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 * 
 * http://www.apache.org/licenses/LICENSE-2.0
 * 
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * @file     dpm32m08x.h
 * @brief    CMSIS HeaderFile
 * @version  1.0
 * @date     10. November 2023
 * @note     Generated by SVDConv V3.3.35 on Friday, 10.11.2023 09:41:21
 *           from File 'dpm32m08x.svd',
 *           last modified on Thursday, 09.11.2023 13:39:28
 */



/** @addtogroup DP Ltd.
  * @{
  */


/** @addtogroup dpm32m08x
  * @{
  */


#ifndef DPM32M08X_H
#define DPM32M08X_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M0 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* =========================================  dpm32m08x Specific Interrupt Numbers  ========================================== */
  WDG_IRQn                  =   0,              /*!< 0  WDG interrupt                                                          */
  PVD_IRQn                  =   1,              /*!< 1  PVD Interrupt                                                          */
  TIM0_IRQn                 =   2,              /*!< 2  TIM0 interrupt                                                         */
  TIM1_IRQn                 =   3,              /*!< 3  TIM1 interrupt                                                         */
  TIM2_3_IRQn               =   4,              /*!< 4  TIM2 and TIM3 interrupt                                                */
  TIM4_5_IRQn               =   5,              /*!< 5  TIM4 and TIM5 interrupt                                                */
  CCT0_IRQn                 =   6,              /*!< 6  CCT0 interrupt                                                         */
  CCT1_IRQn                 =   7,              /*!< 7  CCT1 interrupt                                                         */
  EPWM_IRQn                 =   8,              /*!< 8  EPWM interrupt                                                         */
  POSIF_IRQn                =  10,              /*!< 10 POSIF                                                                  */
  UART0_IRQn                =  12,              /*!< 12 UART0 interrupt                                                        */
  UART1_IRQn                =  13,              /*!< 13 UART1 interrupt                                                        */
  UART2_IRQn                =  14,              /*!< 14 UART2 interrupt                                                        */
  SPI0_IRQn                 =  15,              /*!< 15 SPI0 interrupt                                                         */
  SPI1_IRQn                 =  16,              /*!< 16 SPI1 interrupt                                                         */
  I2C_IRQn                  =  17,              /*!< 17 I2C interrupt                                                          */
  DMA_IRQn                  =  18,              /*!< 18 DMA interrupt                                                          */
  CAN_IRQn                  =  19,              /*!< 19 CAN Interrupt                                                          */
  LPTIM_IRQn                =  20,              /*!< 20 LPTIM Interrupt                                                        */
  ADC0_IRQn                 =  21,              /*!< 21 ADC0 interrupt                                                         */
  ADC1_IRQn                 =  22,              /*!< 22 ADC1 interrupt                                                         */
  GPIOA_IRQn                =  23,              /*!< 23 GPIOA interrupt                                                        */
  GPIOB_IRQn                =  24,              /*!< 24 GPIOB interrupt                                                        */
  GPIOC_D_IRQn              =  25,              /*!< 25 GPIOC and GPIOD interrupt                                              */
  DSP_IRQn                  =  27,              /*!< 27 DSP interrupt                                                          */
  ACMP_IRQn                 =  28               /*!< 28 ACMP Interrupt                                                         */
} IRQn_Type;



/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ===========================  Configuration of the ARM Cortex-M0 Processor and Core Peripherals  =========================== */
#define __CM0_REV                 0x0000U       /*!< CM0 Core Revision                                                         */
#define __NVIC_PRIO_BITS               2        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __MPU_PRESENT                  0        /*!< MPU present                                                               */
#define __FPU_PRESENT                  0        /*!< FPU present                                                               */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0.h"                           /*!< ARM Cortex-M0 processor and core peripherals                              */
#include "system_dpm32m0xx.h"                   /*!< dpm32m0xx System                                                          */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif

/* bit operations */
#define REG32(addr)         (*(volatile unsigned int *)(unsigned int)(addr))
#define REG16(addr)         (*(volatile unsigned short *)(unsigned int)(addr))
#define REG8(addr)          (*(volatile unsigned char *)(unsigned int)(addr))

/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language = extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#elif defined(__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif

#ifdef ASSERT_DEBUG
  /**
   * @brief  The PARAM_ASSERT macro is used for function's parameters check.
   * @param  expr: If expr is false, it calls Param_AssertHandler function
   *         which reports the name of the source file and the source
   *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   **/
#define PARAM_ASSERT(x)                                                   \
  do                                                                      \
  {                                                                       \
    ((x) ? (void)0 : Param_AssertHandler((uint8_t *)__FILE__, __LINE__)); \
  } while (0)
  /* Exported function */
  __attribute__((weak)) void Param_AssertHandler(uint8_t *file, int16_t line);
#else
#define PARAM_ASSERT(x) (void)(0)
#endif /* ASSERT_DEBUG */

  /**
  ******************************************************************************
  * @brief functional state enumeration
  *****************************************************************************/
  typedef enum
  {
    DISABLE = 0,
    ENABLE = !DISABLE
  } FunctionalState;

  /**
  ******************************************************************************
  * @brief Error status enumeration
  *****************************************************************************/
  typedef enum
  {
    ERROR = 0,
    SUCCESS = !ERROR
  } ErrorState;

  /**
  ******************************************************************************
  * @brief Flag status enumeration
  *****************************************************************************/
  typedef enum
  {
    RESET = 0,
    SET = !RESET
  } FlagState;

#define IS_FUNCTION_STATE(x) (((x) == DISABLE) || \
                              ((x) == ENABLE))

#undef NULL
#define NULL 0 /* see <stddef.h> */

/*! Memory clear */
#define MEM_CLEAR_STRUCT(x)                \
  do                                       \
  {                                        \
    memset((void *)&(x), 0L, (sizeof(x))); \
  } while (0);

/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief General-purpose I/Os (GPIO)
  */

typedef struct {                                /*!< (@ 0x40080000) GPIOA Structure                                            */
  __IOM uint32_t  MODE;                         /*!< (@ 0x00000000) GPIOx port mode register (x= A,B,C,D) MODEi[1:0]
                                                                    (i=0~15): 00: General input mode 01: General
                                                                    output mode  10: Alternate function mode
                                                                    11: Analog mode                                            */
  __IOM uint32_t  OUT_TYPE;                     /*!< (@ 0x00000004) GPIOx port output type register (x= A,B,C,D)
                                                                    OTYPEi (i=0~15): 0: Output pull_push 1:
                                                                    Output open_drain                                          */
  __IOM uint32_t  OUT_SPEED;                    /*!< (@ 0x00000008) GPIOx port output speed register (x= A,B,C,D)
                                                                    OSPEEDi (i=0~15): 00: Very low speed 01:
                                                                    Low speed 10: High speed 11: Very high speed               */
  __IOM uint32_t  PUPD;                         /*!< (@ 0x0000000C) GPIOx port pull up/pull down register (x= A,B,C,D)
                                                                    PUPD[1:0]i (i=0~15): 00: No pull up, pull
                                                                    down 01: Pull-up 10: Pull-down 11: Reserved                */
  __IM  uint32_t  DATA_IN;                      /*!< (@ 0x00000010) GPIOx port input data register(x= A,B,C,D)                 */
  __IOM uint32_t  DATA_OUT;                     /*!< (@ 0x00000014) GPIOx port output data register(x= A,B,C,D)                */
  __OM  uint32_t  BIT_SET_RST;                  /*!< (@ 0x00000018) GPIOx port output data bit set/reset register(x=
                                                                    A,B,C,D) Set SETi to 1 will set DOUTi to
                                                                    1 (i=0~15) Set RSTi to 1 will reset DOUTi
                                                                    to 0 (i=0~15) When set both SETi and RSTi
                                                                    to 1 for the same pin, then SETi has a higher
                                                                    priority.                                                  */
  __OM  uint32_t  BIT_RST;                      /*!< (@ 0x0000001C) GPIOx port output data bit reset register(x=
                                                                    A,B,C,D) Set RSTi to 1 will reset DOUTi
                                                                    to 0 (i=0~15)                                              */
  __IOM uint32_t  LOCK;                         /*!< (@ 0x00000020) GPIOx port configuration Lock register (x= A,B,C,D)        */
  __IOM uint32_t  AF_LOW;                       /*!< (@ 0x00000024) GPIOx alternate function low register(x= A,B,C,D)
                                                                    AFSELi[3:0] (i=0~7): 0000: AF0 0001: AF1
                                                                    0010: AF2 0011: AF3 0100: AF4 0101: AF5
                                                                    0110: AF6 0111: AF7 1xxx: Reserved.                        */
  __IOM uint32_t  AF_HIGH;                      /*!< (@ 0x00000028) GPIOx alternate function high register(x= A,B,C,D)
                                                                    AFSELi[3:0] (i=15~8): 0000: AF0 0001: AF1
                                                                    0010: AF2 0011: AF3 0100: AF4 0101: AF5
                                                                    0110: AF6 0111: AF7 1xxx: Reserved.                        */
  __IOM uint32_t  ANA_AF;                       /*!< (@ 0x0000002C) GPIOx analog alternate function register(x= A,B,C,D)
                                                                    ANA_AFSELi[1:0] (i=15~0): 00: AF0 01: AF1
                                                                    10: Reserved. 11: Reserved.                                */
  __IOM uint32_t  INT_EN;                       /*!< (@ 0x00000030) GPIOx interrupts enable register(x= A,B,C,D)
                                                                    IEi (i=15~0): 0: disable interrupt 1: enable
                                                                    interrupt                                                  */
  __IOM uint32_t  INT_TYPE_LOW;                 /*!< (@ 0x00000034) GPIOx interrupts type low register(x= A,B,C,D)
                                                                    INT_TYPEi (i=7~0): 000: Rising edge 001:
                                                                    Falling edge 010: High level 011: Low level
                                                                    100: Rising edge abd Falling edge 101~111:
                                                                    Reserved.                                                  */
  __IOM uint32_t  INT_TYPE_HIGH;                /*!< (@ 0x00000038) GPIOx interrupts type high register(x= A,B,C,D)
                                                                    INT_TYPEi (i=15~8): 000: Rising edge 001:
                                                                    Falling edge 010: High level 011: Low level
                                                                    100: Rising edge abd Falling edge 101~111:
                                                                    Reserved.                                                  */
  __IOM uint32_t  INT_SR;                       /*!< (@ 0x0000003C) GPIOx interrupts status register(x= A,B,C,D)
                                                                    INTi (i=15~0): 0: no interrupt occur 1:
                                                                    interrupt occured                                          */
} GPIO_Type;                                    /*!< Size = 64 (0x40)                                                          */



/* =========================================================================================================================== */
/* ================                                           UART                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief UART register (UART)
  */

typedef struct {                                /*!< (@ 0x40008000) UART0 Structure                                            */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) UART control register                                      */
  __IOM uint32_t  ISR;                          /*!< (@ 0x00000004) UART interrupt and state register                          */
  __IOM uint32_t  BRR;                          /*!< (@ 0x00000008) UART baud rate register                                    */
  __IOM uint32_t  TDR;                          /*!< (@ 0x0000000C) UART transmit data register                                */
  __IM  uint32_t  RDR;                          /*!< (@ 0x00000010) UART reception data register                               */
} UART_Type;                                    /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                            RCC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Reset and Clock Control (RCC)
  */

typedef struct {                                /*!< (@ 0x40001000) RCC Structure                                              */
  __IOM uint32_t  COMMON_CR;                    /*!< (@ 0x00000000) RCC clock common configuration register                    */
  __IOM uint32_t  CLKEN_CR;                     /*!< (@ 0x00000004) RCC clock enable control register                          */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  LPM_CR;                       /*!< (@ 0x00000010) RCC low power mode control register                        */
  __IOM uint32_t  DEEP_SLEEP_CR;                /*!< (@ 0x00000014) RCC deep sleep mode control register                       */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  STOP_CR;                      /*!< (@ 0x0000001C) RCC stop mode control register                             */
  __IM  uint32_t  RESERVED2;
  __IOM uint32_t  RESET_SR;                     /*!< (@ 0x00000024) RCC reset source state register                            */
  __IM  uint32_t  RESERVED3;
  __IOM uint32_t  SYSTEM_CR;                    /*!< (@ 0x0000002C) RCC system control register                                */
  __IOM uint32_t  LOCK_CR;                      /*!< (@ 0x00000030) RCC lock control register                                  */
  __IM  uint32_t  RESERVED4[11];
  __IOM uint32_t  PLL_CR;                       /*!< (@ 0x00000060) RCC pll control register                                   */
} RCC_Type;                                     /*!< Size = 100 (0x64)                                                         */



/* =========================================================================================================================== */
/* ================                                            PGA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief PGA register (PGA)
  */

typedef struct {                                /*!< (@ 0x40001064) PGA Structure                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) PGA control register                                       */
} PGA_Type;                                     /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                            DBG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Debug Support (DBG)
  */

typedef struct {                                /*!< (@ 0x40001028) DBG Structure                                              */
  __IOM uint32_t  CFG;                          /*!< (@ 0x00000000) DBG configuration register                                 */
} DBG_Type;                                     /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                            DES                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Device Electronic Signature (DES)
  */

typedef struct {                                /*!< (@ 0x10001C10) DES Structure                                              */
  __IM  uint32_t  UID_WORD0;                    /*!< (@ 0x00000000) Unique Device ID Word 0                                    */
  __IM  uint32_t  UID_WORD1;                    /*!< (@ 0x00000004) Unique Device ID Word 1                                    */
  __IM  uint32_t  UID_WORD2;                    /*!< (@ 0x00000008) Unique Device ID Word 2                                    */
  __IM  uint32_t  DEV_INFO0;                    /*!< (@ 0x0000000C) Device information 0 register                              */
  __IM  uint32_t  DEV_INFO1;                    /*!< (@ 0x00000010) Device information 1 register                              */
} DES_Type;                                     /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                           TIM                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Basic-timers (TIM)
  */

typedef struct {                                /*!< (@ 0x40019000) TIM0 Structure                                             */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000000) TIMx_CNT_VALUE                                             */
  __IOM uint32_t  ARR;                          /*!< (@ 0x00000004) Auto-reload value                                          */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000008) TIMx_CTRL                                                  */
  __IOM uint32_t  SR;                           /*!< (@ 0x0000000C) TIMx_STATUS                                                */
} TIM_Type;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                           CCT0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Capture/Compare Timer (CCT)
  */

typedef struct {                                /*!< (@ 0x4001F000) CCT0 Structure                                             */
  __IM  uint32_t  CNT;                          /*!< (@ 0x00000000) CCTx_CNTR_VALUE                                            */
  __IOM uint32_t  ARR;                          /*!< (@ 0x00000004) CCTx _LOAD_VALUE                                           */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000008) CCTx_CTRL                                                  */
  __IOM uint32_t  SR;                           /*!< (@ 0x0000000C) CCTx_STATUS                                                */
  __IOM uint32_t  CAP_CFG;                      /*!< (@ 0x00000010) CCTx_CAP_CFG                                               */
  __IOM uint32_t  CMP_CFG;                      /*!< (@ 0x00000014) CCTx_CMP_CFG                                               */
  __IOM uint32_t  CH0_VALUE;                    /*!< (@ 0x00000018) CCTx_CH0_VALUE                                             */
  __IOM uint32_t  CH1_VALUE;                    /*!< (@ 0x0000001C) CCTx_CH1_VALUE                                             */
} CCT_Type;                                     /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                           EPWM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief EPWM registers (EPWM)
  */

typedef struct {                                /*!< (@ 0x40023000) EPWM Structure                                             */
  __IM  uint32_t  CNT;                          /*!< (@ 0x00000000) Counter value                                              */
  __IOM uint32_t  ARR;                          /*!< (@ 0x00000004) Auto-reload value register                                 */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000008) Control register                                           */
  __IOM uint32_t  SR;                           /*!< (@ 0x0000000C) Status register                                            */
  __IOM uint32_t  CMP_CFG;                      /*!< (@ 0x00000010) Comparison value configuration                             */
  __IOM uint32_t  ADC_CMP1;                     /*!< (@ 0x00000014) ADC comparison value 1                                     */
  __IOM uint32_t  ADC_CMP2;                     /*!< (@ 0x00000018) ADC comparison value 2                                     */
  __IOM uint32_t  CH0_CMP1;                     /*!< (@ 0x0000001C) Channel0 comparison value 1                                */
  __IOM uint32_t  CH0_CMP2;                     /*!< (@ 0x00000020) Channel0 comparison value 2                                */
  __IOM uint32_t  CH1_CMP1;                     /*!< (@ 0x00000024) Channel1 comparison value 1                                */
  __IOM uint32_t  CH1_CMP2;                     /*!< (@ 0x00000028) Channel1 comparison value 2                                */
  __IOM uint32_t  CH2_CMP1;                     /*!< (@ 0x0000002C) Channel2 comparison value 1                                */
  __IOM uint32_t  CH2_CMP2;                     /*!< (@ 0x00000030) Channel2 comparison value 2                                */
  __IOM uint32_t  CH3_CMP1;                     /*!< (@ 0x00000034) Channel3 comparison value 1                                */
  __IOM uint32_t  CH3_CMP2;                     /*!< (@ 0x00000038) Channel3 comparison value 2                                */
  __OM  uint32_t  UPDATE;                       /*!< (@ 0x0000003C) Update shadow registers                                    */
  __IOM uint32_t  CH_CR;                        /*!< (@ 0x00000040) Channel control                                            */
  __IOM uint32_t  OUT_CR;                       /*!< (@ 0x00000044) Output control register                                    */
  __IOM uint32_t  DT_CR;                        /*!< (@ 0x00000048) Dead zone time control register                            */
  __IOM uint32_t  STOP_CR;                      /*!< (@ 0x0000004C) Stop control register                                      */
  __IOM uint32_t  STOP_SR;                      /*!< (@ 0x00000050) Stop status register                                       */
  __IOM uint32_t  LOCK;                         /*!< (@ 0x00000054) Lock register                                              */
} EPWM_Type;                                    /*!< Size = 88 (0x58)                                                          */



/* =========================================================================================================================== */
/* ================                                            WDG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Watchdog registers (WDG)
  */

typedef struct {                                /*!< (@ 0x40027000) WDG Structure                                              */
  __IOM uint32_t  CSR;                          /*!< (@ 0x00000000) WDG_CONT_STATUE                                            */
  __OM  uint32_t  CLR;                          /*!< (@ 0x00000004) WDG_CLEAR                                                  */
} WDG_Type;                                     /*!< Size = 8 (0x8)                                                            */



/* =========================================================================================================================== */
/* ================                                           POSIF                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief POSIF registers (POSIF)
  */

typedef struct {                                /*!< (@ 0x40029000) POSIF Structure                                            */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) Control register                                           */
  __IOM uint32_t  ENC_CR;                       /*!< (@ 0x00000004) Encoder control register                                   */
  __IOM uint32_t  ENC_SR;                       /*!< (@ 0x00000008) Encoder status register                                    */
  __IOM uint32_t  ENC_MAX_POS;                  /*!< (@ 0x0000000C) Encoder maximum position count value register              */
  __IOM uint32_t  ENC_CUR_POS;                  /*!< (@ 0x00000010) Encoder current position count value register              */
  __IOM uint32_t  ENC_PULSE_CNT;                /*!< (@ 0x00000014) Encoder pulse counter                                      */
  __IOM uint32_t  HALL_CR;                      /*!< (@ 0x00000018) Hall control register                                      */
  __IOM uint32_t  HALL_SR;                      /*!< (@ 0x0000001C) Hall status register                                       */
  __IM  uint32_t  HALL_WIDTH;                   /*!< (@ 0x00000020) Hall width counter                                         */
  __IOM uint32_t  HALL_MAX_WIDTH;               /*!< (@ 0x00000024) Hall max width value                                       */
  __IOM uint32_t  HALL_DELAY;                   /*!< (@ 0x00000028) Hall status update delay time                              */
} POSIF_Type;                                   /*!< Size = 44 (0x2c)                                                          */



/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief DMA registers (DMA)
  */

typedef struct {                                /*!< (@ 0x4003D000) DMA Structure                                              */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000000) DMA channel status                                         */
  __IOM uint32_t  CH0_CFG0;                     /*!< (@ 0x00000004) Channel 0 configuration register 0                         */
  __IOM uint32_t  CH0_CFG1;                     /*!< (@ 0x00000008) Channel 0 configuration register 1                         */
  __IOM uint32_t  CH0_SRC_ADDR;                 /*!< (@ 0x0000000C) Channel 0 source address                                   */
  __IOM uint32_t  CH0_DST_ADDR;                 /*!< (@ 0x00000010) Channel 0 destination address                              */
  __IOM uint32_t  CH1_CFG0;                     /*!< (@ 0x00000014) Channel 1 configuration register 0                         */
  __IOM uint32_t  CH1_CFG1;                     /*!< (@ 0x00000018) Channel 1 configuration register 1                         */
  __IOM uint32_t  CH1_SRC_ADDR;                 /*!< (@ 0x0000001C) Channel 1 source address                                   */
  __IOM uint32_t  CH1_DST_ADDR;                 /*!< (@ 0x00000020) Channel 1 destination address                              */
  __IOM uint32_t  CH2_CFG0;                     /*!< (@ 0x00000024) Channel 2 configuration register 0                         */
  __IOM uint32_t  CH2_CFG1;                     /*!< (@ 0x00000028) Channel 2 configuration register 1                         */
  __IOM uint32_t  CH2_SRC_ADDR;                 /*!< (@ 0x0000002C) Channel 2 source address                                   */
  __IOM uint32_t  CH2_DST_ADDR;                 /*!< (@ 0x00000030) Channel 2 destination address                              */
  __IOM uint32_t  CH3_CFG0;                     /*!< (@ 0x00000034) Channel 3 configuration register 0                         */
  __IOM uint32_t  CH3_CFG1;                     /*!< (@ 0x00000038) Channel 3 configuration register 1                         */
  __IOM uint32_t  CH3_SRC_ADDR;                 /*!< (@ 0x0000003C) Channel 3 source address                                   */
  __IOM uint32_t  CH3_DST_ADDR;                 /*!< (@ 0x00000040) Channel 3 destination address                              */
  __IOM uint32_t  CH4_CFG0;                     /*!< (@ 0x00000044) Channel 4 configuration register 0                         */
  __IOM uint32_t  CH4_CFG1;                     /*!< (@ 0x00000048) Channel 4 configuration register 1                         */
  __IOM uint32_t  CH4_SRC_ADDR;                 /*!< (@ 0x0000004C) Channel 4 source address                                   */
  __IOM uint32_t  CH4_DST_ADDR;                 /*!< (@ 0x00000050) Channel 4 destination address                              */
} DMA_Type;                                     /*!< Size = 84 (0x54)                                                          */



/* =========================================================================================================================== */
/* ================                                            DSP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Motor Turbo DSP (DSP)
  */

typedef struct {                                /*!< (@ 0x40088000) DSP Structure                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) DSP control register                                       */
  __IOM uint32_t  START;                        /*!< (@ 0x00000004) DSP start trigger register                                 */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000008) DSP status register                                        */
  __IOM uint32_t  EWDG;                         /*!< (@ 0x0000000C) DSP watchdog timer configuration register                  */
  __IOM uint32_t  DEBUG;                        /*!< (@ 0x00000010) DSP debug control register                                 */
  __IM  uint32_t  RESERVED[11];
  __IOM uint32_t  GPR[16];                      /*!< (@ 0x00000040) General-purpose register x                                 */
  __IOM uint32_t  SDR[32];                      /*!< (@ 0x00000080) Static data register x                                     */
  __IM  uint32_t  RESERVED1[192];
  __IOM uint32_t  INS[256];                     /*!< (@ 0x00000400) Instruction memory x                                       */
} DSP_Type;                                     /*!< Size = 2048 (0x800)                                                       */



/* =========================================================================================================================== */
/* ================                                           LPTIM                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief LPTIM (LPTIM)
  */

typedef struct {                                /*!< (@ 0x4002D000) LPTIM Structure                                            */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) LPTIM_CTRL                                                 */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000004) LPTIM_STATUS                                               */
  __IM  uint32_t  WAKEUP_CR;                    /*!< (@ 0x00000008) LPTIM_WAKEUP_CNTR                                          */
  __IOM uint32_t  WAKEUP_PERIOD;                /*!< (@ 0x0000000C) LPTIM WAKEUP PERIOD                                        */
} LPTIM_Type;                                   /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                           SPI                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief SPI (SPI)
  */

typedef struct {                                /*!< (@ 0x4000E000) SPI0 Structure                                             */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) SPI control register                                       */
  __IOM uint32_t  ISR;                          /*!< (@ 0x00000004) SPI interrupt and state register                           */
  __IOM uint32_t  BRR;                          /*!< (@ 0x00000008) SPI baud rate register                                     */
  __IOM uint32_t  TDR;                          /*!< (@ 0x0000000C) SPI trasmit data register                                  */
  __IM  uint32_t  RDR;                          /*!< (@ 0x00000010) SPI receive data register                                  */
} SPI_Type;                                     /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Cyclic Redundancy Check Unit (CRC)
  */

typedef struct {                                /*!< (@ 0x4003C000) CRC Structure                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) CRC_CTRL                                                   */
  __IOM uint32_t  DATA;                         /*!< (@ 0x00000004) CRC_DATA                                                   */
  __IOM uint32_t  INIT;                         /*!< (@ 0x00000008) CRC_INIT                                                   */
  __IM  uint32_t  RESULT;                       /*!< (@ 0x0000000C) CRC_RESULT                                                 */
} CRC_Type;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            DAC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief DAC (DAC)
  */

typedef struct {                                /*!< (@ 0x40035000) DAC Structure                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) DAC Control Register                                       */
  __IOM uint32_t  DR;                           /*!< (@ 0x00000004) DAC channel 12-bit data register                           */
} DAC_Type;                                     /*!< Size = 8 (0x8)                                                            */



/* =========================================================================================================================== */
/* ================                                          ADC_COM                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief ADC COM REG (ADC_COM)
  */

typedef struct {                                /*!< (@ 0x40033000) ADC_COM Structure                                          */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) ADC Common Control Register                                */
  __IOM uint32_t  SMPT;                         /*!< (@ 0x00000004) ADC Channel Sample Time Register                           */
  __IOM uint32_t  SMPC;                         /*!< (@ 0x00000008) ADC Channel Oversampling and Precision Register            */
  __IM  uint32_t  RESERVED[5];
  __IOM uint32_t  CH_OFFSET[16];                /*!< (@ 0x00000020) ADC Channel Offset Value Register x (x=0~15)               */
} ADC_COM_Type;                                 /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                           ADC                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief ADC registers (ADC)
  */

typedef struct {                                /*!< (@ 0x40033100) ADC0 Structure                                             */
  __IOM uint32_t  ISR;                          /*!< (@ 0x00000000) ADC Interrupt State Register                               */
  __IOM uint32_t  IE;                           /*!< (@ 0x00000004) ADC Interrupt Enable Register                              */
  __IOM uint32_t  CFG;                          /*!< (@ 0x00000008) ADC Configuration Register                                 */
  __IOM uint32_t  FMT_CR;                       /*!< (@ 0x0000000C) ADC Format Config Register                                 */
  __IOM uint32_t  TRIG_CR;                      /*!< (@ 0x00000010) ADC Trigger Control Register                               */
  __IOM uint32_t  INJ_CR;                       /*!< (@ 0x00000014) ADC Inject Control Register                                */
  __IOM uint32_t  AWD_CR;                       /*!< (@ 0x00000018) ADC Analog Watch Dog Enable Register                       */
  __IOM uint32_t  AWD_TH;                       /*!< (@ 0x0000001C) ADC Analog Watch Dog Trigger Register                      */
  __IOM uint32_t  SCAN_SQR0;                    /*!< (@ 0x00000020) ADC Channel Sample Sequence Register 0                     */
  __IOM uint32_t  SCAN_SQR1;                    /*!< (@ 0x00000024) ADC Channel Sample Sequence Register 1                     */
  __IM  uint32_t  DR_SINGLE;                    /*!< (@ 0x00000028) ADC Single Sample Data Register                            */
  __IM  uint32_t  DR_INJ;                       /*!< (@ 0x0000002C) ADC Inject Sample Data Register                            */
  __IM  uint32_t  DR_TRIG0;                     /*!< (@ 0x00000030) ADC Trigger Sample Data Register 0                         */
  __IM  uint32_t  DR_TRIG1;                     /*!< (@ 0x00000034) ADC Trigger Sample Data Register 1                         */
  __IM  uint32_t  DR_SCAN[14];                  /*!< (@ 0x00000038) ADC Sequence Sample Data Register n (n=0~13)               */
} ADC_Type;                                     /*!< Size = 112 (0x70)                                                         */



/* =========================================================================================================================== */
/* ================                                            I2C                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief I2C registers (I2C)
  */

typedef struct {                                /*!< (@ 0x40012000) I2C Structure                                              */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) I2C control register 1                                     */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) I2C control register 2                                     */
  __IOM uint32_t  ISR;                          /*!< (@ 0x00000008) I2C interrupt and status register                          */
  __IOM uint32_t  TIMING;                       /*!< (@ 0x0000000C) I2C timing register                                        */
  __IOM uint32_t  OAR;                          /*!< (@ 0x00000010) I2C own address register                                   */
  __IOM uint32_t  TDR;                          /*!< (@ 0x00000014) I2C Transmit data register                                 */
  __IM  uint32_t  RDR;                          /*!< (@ 0x00000018) I2C Receive data register                                  */
} I2C_Type;                                     /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                           ACMP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog Comparator (ACMP)
  */

typedef struct {                                /*!< (@ 0x4003A000) ACMP Structure                                             */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) ACMP control register                                      */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000004) ACMP status register                                       */
  __IOM uint32_t  ACMP0_CFG;                    /*!< (@ 0x00000008) ACMP0 configuration register                               */
  __IOM uint32_t  ACMP1_CFG;                    /*!< (@ 0x0000000C) ACMP1 configuration register                               */
  __IOM uint32_t  ACMP2_CFG;                    /*!< (@ 0x00000010) ACMP2 configuration register                               */
  __IOM uint32_t  ACMP3_CFG;                    /*!< (@ 0x00000014) ACMP3 configuration register                               */
} ACMP_Type;                                    /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Flash Controler (FLASH)
  */

typedef struct {                                /*!< (@ 0x40089000) FLASH Structure                                            */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) Flash control register                                     */
  __IOM uint32_t  ADDR;                         /*!< (@ 0x00000004) Flash program or page erase address register               */
  __IOM uint32_t  DATA;                         /*!< (@ 0x00000008) Flash program data register                                */
  __IOM uint32_t  CR_LOCK;                      /*!< (@ 0x0000000C) Flash config registers lock register                       */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000010) Flash status register                                      */
  __IOM uint32_t  FAC_REC;                      /*!< (@ 0x00000014) Flash factory mode recovery register                       */
} FLASH_Type;                                   /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                            PVD                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Power Voltage Detector (PVD)
  */

typedef struct {                                /*!< (@ 0x40039000) PVD Structure                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) PVD_CR                                                     */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000004) PVD_SR                                                     */
} PVD_Type;                                     /*!< Size = 8 (0x8)                                                            */



/* =========================================================================================================================== */
/* ================                                           CAN                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Control Area Network in Basic Mode (CAN)
  */

typedef union {                                 /*!< (@ 0x40014000) CAN Structure                                              */
    struct {
      __IOM uint32_t  CTRL;                     /*!< (@ 0x00000000) CAN_Ctrl                                                   */
      __OM  uint32_t  COMMAND;                  /*!< (@ 0x00000004) CAN_Command                                                */
      __IM  uint32_t  STATUS;                   /*!< (@ 0x00000008) CAN_STATUS                                                 */
      __IM  uint32_t  INTERRUPT;                /*!< (@ 0x0000000C) CAN_Interrupt                                              */
      __IOM uint32_t  ACR;                      /*!< (@ 0x00000010) Acceptance Code Register                                   */
      __IOM uint32_t  AMR;                      /*!< (@ 0x00000014) Acceptance Mask Register                                   */
      __IOM uint32_t  BTR0;                     /*!< (@ 0x00000018) Bus_Timing_Register0                                       */
      __IOM uint32_t  BTR1;                     /*!< (@ 0x0000001C) Bus_Timing_Register1                                       */
      __IM  uint32_t  RESERVED[2];
      __OM  uint32_t  TX_ID_BYTE1;              /*!< (@ 0x00000028) Transmit Buffer Identifier Byte1                           */
      __OM  uint32_t  TX_ID_BYTE2;              /*!< (@ 0x0000002C) Transmit Buffer Identifier Byte2                           */
      __OM  uint32_t  TX_DATA1;                 /*!< (@ 0x00000030) Transmit data byte1                                        */
      __OM  uint32_t  TX_DATA2;                 /*!< (@ 0x00000034) Transmit data byte2                                        */
      __OM  uint32_t  TX_DATA3;                 /*!< (@ 0x00000038) Transmit data byte3                                        */
      __OM  uint32_t  TX_DATA4;                 /*!< (@ 0x0000003C) Transmit data byte4                                        */
      __OM  uint32_t  TX_DATA5;                 /*!< (@ 0x00000040) Transmit data byte5                                        */
      __OM  uint32_t  TX_DATA6;                 /*!< (@ 0x00000044) Transmit data byte6                                        */
      __OM  uint32_t  TX_DATA7;                 /*!< (@ 0x00000048) Transmit data byte7                                        */
      __OM  uint32_t  TX_DATA8;                 /*!< (@ 0x0000004C) Transmit data byte8                                        */
      __IM  uint32_t  RX_ID_BYTE1;              /*!< (@ 0x00000050) RX Buffer Identifier Byte 1                                */
      __IM  uint32_t  RX_ID_BYTE2;              /*!< (@ 0x00000054) RX Buffer Identifier Byte 2                                */
      __IM  uint32_t  RX_DATA1;                 /*!< (@ 0x00000058) Receive Data Byte 1                                        */
      __IM  uint32_t  RX_DATA2;                 /*!< (@ 0x0000005C) Receive Data Byte 2                                        */
      __IM  uint32_t  RX_DATA3;                 /*!< (@ 0x00000060) Receive Data Byte 3                                        */
      __IM  uint32_t  RX_DATA4;                 /*!< (@ 0x00000064) Receive Data Byte 4                                        */
      __IM  uint32_t  RX_DATA5;                 /*!< (@ 0x00000068) Receive Data Byte 5                                        */
      __IM  uint32_t  RX_DATA6;                 /*!< (@ 0x0000006C) Receive Data Byte 6                                        */
      __IM  uint32_t  RX_DATA7;                 /*!< (@ 0x00000070) Receive Data Byte 7                                        */
      __IM  uint32_t  RX_DATA8;                 /*!< (@ 0x00000074) Receive Data Byte 8                                        */
      __IM  uint32_t  RESERVED1;
      __IOM uint32_t  EX_CAN;                   /*!< (@ 0x0000007C) EXTENDED_CAN                                               */
    } CAN_BASEMODE;

    struct {
      __IOM uint32_t  MODE;                     /*!< (@ 0x00000000) CAN_Mode                                                   */
      __OM  uint32_t  COMMAND;                  /*!< (@ 0x00000004) CAN_Command                                                */
      __IM  uint32_t  STATUS;                   /*!< (@ 0x00000008) CAN_STATUS                                                 */
      __IM  uint32_t  INTERRUPT;                /*!< (@ 0x0000000C) CAN_Interrupt                                              */
      __IOM uint32_t  IE;                       /*!< (@ 0x00000010) Interrupt Enable                                           */
      __IM  uint32_t  RESERVED;
      __IOM uint32_t  BTR0;                     /*!< (@ 0x00000018) Bus_Timing_Register0                                       */
      __IOM uint32_t  BTR1;                     /*!< (@ 0x0000001C) Bus_Timing1_Register                                       */
      __IM  uint32_t  RESERVED1[3];
      __IM  uint32_t  ALC;                      /*!< (@ 0x0000002C) Arbitration lost capture                                   */
      __IM  uint32_t  ECC;                      /*!< (@ 0x00000030) Error code capture                                         */
      __IOM uint32_t  EWL;                      /*!< (@ 0x00000034) Error Warning Limit                                        */
      __IOM uint32_t  RX_ERR;                   /*!< (@ 0x00000038) Receive error counter                                      */
      __IOM uint32_t  TX_ERR;                   /*!< (@ 0x0000003C) Transmit error counter                                     */
      __IOM uint32_t  FRAME_INFO;               /*!< (@ 0x00000040) Frame information                                          */
      __IOM uint32_t  ID1;                      /*!< (@ 0x00000044) Identifier 1                                               */
      __IOM uint32_t  ID2;                      /*!< (@ 0x00000048) Identifier 2                                               */
      __IOM uint32_t  DATA1_ID3;                /*!< (@ 0x0000004C) data byte 1 in SFF or identifier 3 in EFF                  */
      __IOM uint32_t  DATA2_ID4;                /*!< (@ 0x00000050) data byte 2 in SFF or identifier 4 in EFF                  */
      __IOM uint32_t  DATA3_DA1;                /*!< (@ 0x00000054) data byte 3 in SFF or data byte 1 in EFF                   */
      __IOM uint32_t  DATA4_DA2;                /*!< (@ 0x00000058) data byte 4 in SFF or data byte 2 in EFF                   */
      __IOM uint32_t  DATA5_DA3;                /*!< (@ 0x0000005C) data byte 5 in SFF or data byte 3 in EFF                   */
      __IOM uint32_t  DATA6_DA4;                /*!< (@ 0x00000060) data byte 6 in SFF or data byte 4 in EFF                   */
      __IOM uint32_t  DATA7_DA5;                /*!< (@ 0x00000064) data byte 7 in SFF or data byte 5 in EFF                   */
      __IOM uint32_t  DATA8_DA6;                /*!< (@ 0x00000068) data byte 8 in SFF or data byte 6 in EFF                   */
      __IOM uint32_t  RES_DA7;                  /*!< (@ 0x0000006C) Reserve in SFF or data byte 7 in EFF                       */
      __IOM uint32_t  RES_DA8;                  /*!< (@ 0x00000070) Reserve in SFF or data byte 8 in EFF                       */
      __IM  uint32_t  RMC;                      /*!< (@ 0x00000074) RX Message Counter                                         */
      __IM  uint32_t  RESERVED2;
      __IOM uint32_t  EX_CAN;                   /*!< (@ 0x0000007C) EXTENDED_CAN                                               */
    } CAN_PELIMODE;
} CAN_Type;                                     /*!< Size = 128 (0x80)                                                         */  


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define GPIOA_BASE                  0x40080000UL
#define GPIOB_BASE                  0x40081000UL
#define GPIOC_BASE                  0x40082000UL
#define GPIOD_BASE                  0x40083000UL
#define UART0_BASE                  0x40008000UL
#define UART1_BASE                  0x40009000UL
#define UART2_BASE                  0x4000A000UL
#define RCC_BASE                    0x40001000UL
#define PGA_BASE                    0x40001064UL
#define DBG_BASE                    0x40001028UL
#define DES_BASE                    0x10001C10UL
#define TIM0_BASE                   0x40019000UL
#define TIM1_BASE                   0x4001A000UL
#define TIM2_BASE                   0x4001B000UL
#define TIM3_BASE                   0x4001C000UL
#define TIM4_BASE                   0x4001D000UL
#define TIM5_BASE                   0x4001E000UL
#define CCT0_BASE                   0x4001F000UL
#define CCT1_BASE                   0x40020000UL
#define EPWM_BASE                   0x40023000UL
#define WDG_BASE                    0x40027000UL
#define POSIF_BASE                  0x40029000UL
#define DMA_BASE                    0x4003D000UL
#define DSP_BASE                    0x40088000UL
#define LPTIM_BASE                  0x4002D000UL
#define SPI0_BASE                   0x4000E000UL
#define SPI1_BASE                   0x4000F000UL
#define CRC_BASE                    0x4003C000UL
#define DAC_BASE                    0x40035000UL
#define ADC_COM_BASE                0x40033000UL
#define ADC0_BASE                   0x40033100UL
#define ADC1_BASE                   0x40033200UL
#define I2C_BASE                    0x40012000UL
#define ACMP_BASE                   0x4003A000UL
#define FLASH_BASE                  0x40089000UL
#define PVD_BASE                    0x40039000UL
#define CAN_BASE                    0x40014000UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define GPIOA                       ((GPIO_Type*)              GPIOA_BASE)
#define GPIOB                       ((GPIO_Type*)              GPIOB_BASE)
#define GPIOC                       ((GPIO_Type*)              GPIOC_BASE)
#define GPIOD                       ((GPIO_Type*)              GPIOD_BASE)
#define UART0                       ((UART_Type*)              UART0_BASE)
#define UART1                       ((UART_Type*)              UART1_BASE)
#define UART2                       ((UART_Type*)              UART2_BASE)
#define RCC                         ((RCC_Type*)               RCC_BASE)
#define PGA                         ((PGA_Type*)               PGA_BASE)
#define DBG                         ((DBG_Type*)               DBG_BASE)
#define DES                         ((DES_Type*)               DES_BASE)
#define TIM0                        ((TIM_Type*)               TIM0_BASE)
#define TIM1                        ((TIM_Type*)               TIM1_BASE)
#define TIM2                        ((TIM_Type*)               TIM2_BASE)
#define TIM3                        ((TIM_Type*)               TIM3_BASE)
#define TIM4                        ((TIM_Type*)               TIM4_BASE)
#define TIM5                        ((TIM_Type*)               TIM5_BASE)
#define CCT0                        ((CCT_Type*)               CCT0_BASE)
#define CCT1                        ((CCT_Type*)               CCT1_BASE)
#define EPWM                        ((EPWM_Type*)              EPWM_BASE)
#define WDG                         ((WDG_Type*)               WDG_BASE)
#define POSIF                       ((POSIF_Type*)             POSIF_BASE)
#define DMA                         ((DMA_Type*)               DMA_BASE)
#define DSP                         ((DSP_Type*)               DSP_BASE)
#define LPTIM                       ((LPTIM_Type*)             LPTIM_BASE)
#define SPI0                        ((SPI_Type*)               SPI0_BASE)
#define SPI1                        ((SPI_Type*)               SPI1_BASE)
#define CRC                         ((CRC_Type*)               CRC_BASE)
#define DAC                         ((DAC_Type*)               DAC_BASE)
#define ADC_COM                     ((ADC_COM_Type*)           ADC_COM_BASE)
#define ADC0                        ((ADC_Type*)               ADC0_BASE)
#define ADC1                        ((ADC_Type*)               ADC1_BASE)
#define I2C                         ((I2C_Type*)               I2C_BASE)
#define ACMP                        ((ACMP_Type*)              ACMP_BASE)
#define FLASH                       ((FLASH_Type*)             FLASH_BASE)
#define PVD                         ((PVD_Type*)               PVD_BASE)
#define CAN                         ((CAN_Type*)               CAN_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */



/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  MODE  ========================================================== */
#define GPIO_MODE_MODE15_Pos              (30UL)                    /*!< MODE15 (Bit 30)                                       */
#define GPIO_MODE_MODE15_Msk              (0xc0000000UL)            /*!< MODE15 (Bitfield-Mask: 0x03)                          */
#define GPIO_MODE_MODE14_Pos              (28UL)                    /*!< MODE14 (Bit 28)                                       */
#define GPIO_MODE_MODE14_Msk              (0x30000000UL)            /*!< MODE14 (Bitfield-Mask: 0x03)                          */
#define GPIO_MODE_MODE13_Pos              (26UL)                    /*!< MODE13 (Bit 26)                                       */
#define GPIO_MODE_MODE13_Msk              (0xc000000UL)             /*!< MODE13 (Bitfield-Mask: 0x03)                          */
#define GPIO_MODE_MODE12_Pos              (24UL)                    /*!< MODE12 (Bit 24)                                       */
#define GPIO_MODE_MODE12_Msk              (0x3000000UL)             /*!< MODE12 (Bitfield-Mask: 0x03)                          */
#define GPIO_MODE_MODE11_Pos              (22UL)                    /*!< MODE11 (Bit 22)                                       */
#define GPIO_MODE_MODE11_Msk              (0xc00000UL)              /*!< MODE11 (Bitfield-Mask: 0x03)                          */
#define GPIO_MODE_MODE10_Pos              (20UL)                    /*!< MODE10 (Bit 20)                                       */
#define GPIO_MODE_MODE10_Msk              (0x300000UL)              /*!< MODE10 (Bitfield-Mask: 0x03)                          */
#define GPIO_MODE_MODE9_Pos               (18UL)                    /*!< MODE9 (Bit 18)                                        */
#define GPIO_MODE_MODE9_Msk               (0xc0000UL)               /*!< MODE9 (Bitfield-Mask: 0x03)                           */
#define GPIO_MODE_MODE8_Pos               (16UL)                    /*!< MODE8 (Bit 16)                                        */
#define GPIO_MODE_MODE8_Msk               (0x30000UL)               /*!< MODE8 (Bitfield-Mask: 0x03)                           */
#define GPIO_MODE_MODE7_Pos               (14UL)                    /*!< MODE7 (Bit 14)                                        */
#define GPIO_MODE_MODE7_Msk               (0xc000UL)                /*!< MODE7 (Bitfield-Mask: 0x03)                           */
#define GPIO_MODE_MODE6_Pos               (12UL)                    /*!< MODE6 (Bit 12)                                        */
#define GPIO_MODE_MODE6_Msk               (0x3000UL)                /*!< MODE6 (Bitfield-Mask: 0x03)                           */
#define GPIO_MODE_MODE5_Pos               (10UL)                    /*!< MODE5 (Bit 10)                                        */
#define GPIO_MODE_MODE5_Msk               (0xc00UL)                 /*!< MODE5 (Bitfield-Mask: 0x03)                           */
#define GPIO_MODE_MODE4_Pos               (8UL)                     /*!< MODE4 (Bit 8)                                         */
#define GPIO_MODE_MODE4_Msk               (0x300UL)                 /*!< MODE4 (Bitfield-Mask: 0x03)                           */
#define GPIO_MODE_MODE3_Pos               (6UL)                     /*!< MODE3 (Bit 6)                                         */
#define GPIO_MODE_MODE3_Msk               (0xc0UL)                  /*!< MODE3 (Bitfield-Mask: 0x03)                           */
#define GPIO_MODE_MODE2_Pos               (4UL)                     /*!< MODE2 (Bit 4)                                         */
#define GPIO_MODE_MODE2_Msk               (0x30UL)                  /*!< MODE2 (Bitfield-Mask: 0x03)                           */
#define GPIO_MODE_MODE1_Pos               (2UL)                     /*!< MODE1 (Bit 2)                                         */
#define GPIO_MODE_MODE1_Msk               (0xcUL)                   /*!< MODE1 (Bitfield-Mask: 0x03)                           */
#define GPIO_MODE_MODE0_Pos               (0UL)                     /*!< MODE0 (Bit 0)                                         */
#define GPIO_MODE_MODE0_Msk               (0x3UL)                   /*!< MODE0 (Bitfield-Mask: 0x03)                           */
/* =======================================================  OUT_TYPE  ======================================================== */
#define GPIO_OUT_TYPE_OTYPE15_Pos         (15UL)                    /*!< OTYPE15 (Bit 15)                                      */
#define GPIO_OUT_TYPE_OTYPE15_Msk         (0x8000UL)                /*!< OTYPE15 (Bitfield-Mask: 0x01)                         */
#define GPIO_OUT_TYPE_OTYPE14_Pos         (14UL)                    /*!< OTYPE14 (Bit 14)                                      */
#define GPIO_OUT_TYPE_OTYPE14_Msk         (0x4000UL)                /*!< OTYPE14 (Bitfield-Mask: 0x01)                         */
#define GPIO_OUT_TYPE_OTYPE13_Pos         (13UL)                    /*!< OTYPE13 (Bit 13)                                      */
#define GPIO_OUT_TYPE_OTYPE13_Msk         (0x2000UL)                /*!< OTYPE13 (Bitfield-Mask: 0x01)                         */
#define GPIO_OUT_TYPE_OTYPE12_Pos         (12UL)                    /*!< OTYPE12 (Bit 12)                                      */
#define GPIO_OUT_TYPE_OTYPE12_Msk         (0x1000UL)                /*!< OTYPE12 (Bitfield-Mask: 0x01)                         */
#define GPIO_OUT_TYPE_OTYPE11_Pos         (11UL)                    /*!< OTYPE11 (Bit 11)                                      */
#define GPIO_OUT_TYPE_OTYPE11_Msk         (0x800UL)                 /*!< OTYPE11 (Bitfield-Mask: 0x01)                         */
#define GPIO_OUT_TYPE_OTYPE10_Pos         (10UL)                    /*!< OTYPE10 (Bit 10)                                      */
#define GPIO_OUT_TYPE_OTYPE10_Msk         (0x400UL)                 /*!< OTYPE10 (Bitfield-Mask: 0x01)                         */
#define GPIO_OUT_TYPE_OTYPE9_Pos          (9UL)                     /*!< OTYPE9 (Bit 9)                                        */
#define GPIO_OUT_TYPE_OTYPE9_Msk          (0x200UL)                 /*!< OTYPE9 (Bitfield-Mask: 0x01)                          */
#define GPIO_OUT_TYPE_OTYPE8_Pos          (8UL)                     /*!< OTYPE8 (Bit 8)                                        */
#define GPIO_OUT_TYPE_OTYPE8_Msk          (0x100UL)                 /*!< OTYPE8 (Bitfield-Mask: 0x01)                          */
#define GPIO_OUT_TYPE_OTYPE7_Pos          (7UL)                     /*!< OTYPE7 (Bit 7)                                        */
#define GPIO_OUT_TYPE_OTYPE7_Msk          (0x80UL)                  /*!< OTYPE7 (Bitfield-Mask: 0x01)                          */
#define GPIO_OUT_TYPE_OTYPE6_Pos          (6UL)                     /*!< OTYPE6 (Bit 6)                                        */
#define GPIO_OUT_TYPE_OTYPE6_Msk          (0x40UL)                  /*!< OTYPE6 (Bitfield-Mask: 0x01)                          */
#define GPIO_OUT_TYPE_OTYPE5_Pos          (5UL)                     /*!< OTYPE5 (Bit 5)                                        */
#define GPIO_OUT_TYPE_OTYPE5_Msk          (0x20UL)                  /*!< OTYPE5 (Bitfield-Mask: 0x01)                          */
#define GPIO_OUT_TYPE_OTYPE4_Pos          (4UL)                     /*!< OTYPE4 (Bit 4)                                        */
#define GPIO_OUT_TYPE_OTYPE4_Msk          (0x10UL)                  /*!< OTYPE4 (Bitfield-Mask: 0x01)                          */
#define GPIO_OUT_TYPE_OTYPE3_Pos          (3UL)                     /*!< OTYPE3 (Bit 3)                                        */
#define GPIO_OUT_TYPE_OTYPE3_Msk          (0x8UL)                   /*!< OTYPE3 (Bitfield-Mask: 0x01)                          */
#define GPIO_OUT_TYPE_OTYPE2_Pos          (2UL)                     /*!< OTYPE2 (Bit 2)                                        */
#define GPIO_OUT_TYPE_OTYPE2_Msk          (0x4UL)                   /*!< OTYPE2 (Bitfield-Mask: 0x01)                          */
#define GPIO_OUT_TYPE_OTYPE1_Pos          (1UL)                     /*!< OTYPE1 (Bit 1)                                        */
#define GPIO_OUT_TYPE_OTYPE1_Msk          (0x2UL)                   /*!< OTYPE1 (Bitfield-Mask: 0x01)                          */
#define GPIO_OUT_TYPE_OTYPE0_Pos          (0UL)                     /*!< OTYPE0 (Bit 0)                                        */
#define GPIO_OUT_TYPE_OTYPE0_Msk          (0x1UL)                   /*!< OTYPE0 (Bitfield-Mask: 0x01)                          */
/* =======================================================  OUT_SPEED  ======================================================= */
#define GPIO_OUT_SPEED_OSPEED15_Pos       (30UL)                    /*!< OSPEED15 (Bit 30)                                     */
#define GPIO_OUT_SPEED_OSPEED15_Msk       (0xc0000000UL)            /*!< OSPEED15 (Bitfield-Mask: 0x03)                        */
#define GPIO_OUT_SPEED_OSPEED14_Pos       (28UL)                    /*!< OSPEED14 (Bit 28)                                     */
#define GPIO_OUT_SPEED_OSPEED14_Msk       (0x30000000UL)            /*!< OSPEED14 (Bitfield-Mask: 0x03)                        */
#define GPIO_OUT_SPEED_OSPEED13_Pos       (26UL)                    /*!< OSPEED13 (Bit 26)                                     */
#define GPIO_OUT_SPEED_OSPEED13_Msk       (0xc000000UL)             /*!< OSPEED13 (Bitfield-Mask: 0x03)                        */
#define GPIO_OUT_SPEED_OSPEED12_Pos       (24UL)                    /*!< OSPEED12 (Bit 24)                                     */
#define GPIO_OUT_SPEED_OSPEED12_Msk       (0x3000000UL)             /*!< OSPEED12 (Bitfield-Mask: 0x03)                        */
#define GPIO_OUT_SPEED_OSPEED11_Pos       (22UL)                    /*!< OSPEED11 (Bit 22)                                     */
#define GPIO_OUT_SPEED_OSPEED11_Msk       (0xc00000UL)              /*!< OSPEED11 (Bitfield-Mask: 0x03)                        */
#define GPIO_OUT_SPEED_OSPEED10_Pos       (20UL)                    /*!< OSPEED10 (Bit 20)                                     */
#define GPIO_OUT_SPEED_OSPEED10_Msk       (0x300000UL)              /*!< OSPEED10 (Bitfield-Mask: 0x03)                        */
#define GPIO_OUT_SPEED_OSPEED9_Pos        (18UL)                    /*!< OSPEED9 (Bit 18)                                      */
#define GPIO_OUT_SPEED_OSPEED9_Msk        (0xc0000UL)               /*!< OSPEED9 (Bitfield-Mask: 0x03)                         */
#define GPIO_OUT_SPEED_OSPEED8_Pos        (16UL)                    /*!< OSPEED8 (Bit 16)                                      */
#define GPIO_OUT_SPEED_OSPEED8_Msk        (0x30000UL)               /*!< OSPEED8 (Bitfield-Mask: 0x03)                         */
#define GPIO_OUT_SPEED_OSPEED7_Pos        (14UL)                    /*!< OSPEED7 (Bit 14)                                      */
#define GPIO_OUT_SPEED_OSPEED7_Msk        (0xc000UL)                /*!< OSPEED7 (Bitfield-Mask: 0x03)                         */
#define GPIO_OUT_SPEED_OSPEED6_Pos        (12UL)                    /*!< OSPEED6 (Bit 12)                                      */
#define GPIO_OUT_SPEED_OSPEED6_Msk        (0x3000UL)                /*!< OSPEED6 (Bitfield-Mask: 0x03)                         */
#define GPIO_OUT_SPEED_OSPEED5_Pos        (10UL)                    /*!< OSPEED5 (Bit 10)                                      */
#define GPIO_OUT_SPEED_OSPEED5_Msk        (0xc00UL)                 /*!< OSPEED5 (Bitfield-Mask: 0x03)                         */
#define GPIO_OUT_SPEED_OSPEED4_Pos        (8UL)                     /*!< OSPEED4 (Bit 8)                                       */
#define GPIO_OUT_SPEED_OSPEED4_Msk        (0x300UL)                 /*!< OSPEED4 (Bitfield-Mask: 0x03)                         */
#define GPIO_OUT_SPEED_OSPEED3_Pos        (6UL)                     /*!< OSPEED3 (Bit 6)                                       */
#define GPIO_OUT_SPEED_OSPEED3_Msk        (0xc0UL)                  /*!< OSPEED3 (Bitfield-Mask: 0x03)                         */
#define GPIO_OUT_SPEED_OSPEED2_Pos        (4UL)                     /*!< OSPEED2 (Bit 4)                                       */
#define GPIO_OUT_SPEED_OSPEED2_Msk        (0x30UL)                  /*!< OSPEED2 (Bitfield-Mask: 0x03)                         */
#define GPIO_OUT_SPEED_OSPEED1_Pos        (2UL)                     /*!< OSPEED1 (Bit 2)                                       */
#define GPIO_OUT_SPEED_OSPEED1_Msk        (0xcUL)                   /*!< OSPEED1 (Bitfield-Mask: 0x03)                         */
#define GPIO_OUT_SPEED_OSPEED0_Pos        (0UL)                     /*!< OSPEED0 (Bit 0)                                       */
#define GPIO_OUT_SPEED_OSPEED0_Msk        (0x3UL)                   /*!< OSPEED0 (Bitfield-Mask: 0x03)                         */
/* =========================================================  PUPD  ========================================================== */
#define GPIO_PUPD_PUPD15_Pos              (30UL)                    /*!< PUPD15 (Bit 30)                                       */
#define GPIO_PUPD_PUPD15_Msk              (0xc0000000UL)            /*!< PUPD15 (Bitfield-Mask: 0x03)                          */
#define GPIO_PUPD_PUPD14_Pos              (28UL)                    /*!< PUPD14 (Bit 28)                                       */
#define GPIO_PUPD_PUPD14_Msk              (0x30000000UL)            /*!< PUPD14 (Bitfield-Mask: 0x03)                          */
#define GPIO_PUPD_PUPD13_Pos              (26UL)                    /*!< PUPD13 (Bit 26)                                       */
#define GPIO_PUPD_PUPD13_Msk              (0xc000000UL)             /*!< PUPD13 (Bitfield-Mask: 0x03)                          */
#define GPIO_PUPD_PUPD12_Pos              (24UL)                    /*!< PUPD12 (Bit 24)                                       */
#define GPIO_PUPD_PUPD12_Msk              (0x3000000UL)             /*!< PUPD12 (Bitfield-Mask: 0x03)                          */
#define GPIO_PUPD_PUPD11_Pos              (22UL)                    /*!< PUPD11 (Bit 22)                                       */
#define GPIO_PUPD_PUPD11_Msk              (0xc00000UL)              /*!< PUPD11 (Bitfield-Mask: 0x03)                          */
#define GPIO_PUPD_PUPD10_Pos              (20UL)                    /*!< PUPD10 (Bit 20)                                       */
#define GPIO_PUPD_PUPD10_Msk              (0x300000UL)              /*!< PUPD10 (Bitfield-Mask: 0x03)                          */
#define GPIO_PUPD_PUPD9_Pos               (18UL)                    /*!< PUPD9 (Bit 18)                                        */
#define GPIO_PUPD_PUPD9_Msk               (0xc0000UL)               /*!< PUPD9 (Bitfield-Mask: 0x03)                           */
#define GPIO_PUPD_PUPD8_Pos               (16UL)                    /*!< PUPD8 (Bit 16)                                        */
#define GPIO_PUPD_PUPD8_Msk               (0x30000UL)               /*!< PUPD8 (Bitfield-Mask: 0x03)                           */
#define GPIO_PUPD_PUPD7_Pos               (14UL)                    /*!< PUPD7 (Bit 14)                                        */
#define GPIO_PUPD_PUPD7_Msk               (0xc000UL)                /*!< PUPD7 (Bitfield-Mask: 0x03)                           */
#define GPIO_PUPD_PUPD6_Pos               (12UL)                    /*!< PUPD6 (Bit 12)                                        */
#define GPIO_PUPD_PUPD6_Msk               (0x3000UL)                /*!< PUPD6 (Bitfield-Mask: 0x03)                           */
#define GPIO_PUPD_PUPD5_Pos               (10UL)                    /*!< PUPD5 (Bit 10)                                        */
#define GPIO_PUPD_PUPD5_Msk               (0xc00UL)                 /*!< PUPD5 (Bitfield-Mask: 0x03)                           */
#define GPIO_PUPD_PUPD4_Pos               (8UL)                     /*!< PUPD4 (Bit 8)                                         */
#define GPIO_PUPD_PUPD4_Msk               (0x300UL)                 /*!< PUPD4 (Bitfield-Mask: 0x03)                           */
#define GPIO_PUPD_PUPD3_Pos               (6UL)                     /*!< PUPD3 (Bit 6)                                         */
#define GPIO_PUPD_PUPD3_Msk               (0xc0UL)                  /*!< PUPD3 (Bitfield-Mask: 0x03)                           */
#define GPIO_PUPD_PUPD2_Pos               (4UL)                     /*!< PUPD2 (Bit 4)                                         */
#define GPIO_PUPD_PUPD2_Msk               (0x30UL)                  /*!< PUPD2 (Bitfield-Mask: 0x03)                           */
#define GPIO_PUPD_PUPD1_Pos               (2UL)                     /*!< PUPD1 (Bit 2)                                         */
#define GPIO_PUPD_PUPD1_Msk               (0xcUL)                   /*!< PUPD1 (Bitfield-Mask: 0x03)                           */
#define GPIO_PUPD_PUPD0_Pos               (0UL)                     /*!< PUPD0 (Bit 0)                                         */
#define GPIO_PUPD_PUPD0_Msk               (0x3UL)                   /*!< PUPD0 (Bitfield-Mask: 0x03)                           */
/* ========================================================  DATA_IN  ======================================================== */
#define GPIO_DATA_IN_DIN15_Pos            (15UL)                    /*!< DIN15 (Bit 15)                                        */
#define GPIO_DATA_IN_DIN15_Msk            (0x8000UL)                /*!< DIN15 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_IN_DIN14_Pos            (14UL)                    /*!< DIN14 (Bit 14)                                        */
#define GPIO_DATA_IN_DIN14_Msk            (0x4000UL)                /*!< DIN14 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_IN_DIN13_Pos            (13UL)                    /*!< DIN13 (Bit 13)                                        */
#define GPIO_DATA_IN_DIN13_Msk            (0x2000UL)                /*!< DIN13 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_IN_DIN12_Pos            (12UL)                    /*!< DIN12 (Bit 12)                                        */
#define GPIO_DATA_IN_DIN12_Msk            (0x1000UL)                /*!< DIN12 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_IN_DIN11_Pos            (11UL)                    /*!< DIN11 (Bit 11)                                        */
#define GPIO_DATA_IN_DIN11_Msk            (0x800UL)                 /*!< DIN11 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_IN_DIN10_Pos            (10UL)                    /*!< DIN10 (Bit 10)                                        */
#define GPIO_DATA_IN_DIN10_Msk            (0x400UL)                 /*!< DIN10 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_IN_DIN9_Pos             (9UL)                     /*!< DIN9 (Bit 9)                                          */
#define GPIO_DATA_IN_DIN9_Msk             (0x200UL)                 /*!< DIN9 (Bitfield-Mask: 0x01)                            */
#define GPIO_DATA_IN_DIN8_Pos             (8UL)                     /*!< DIN8 (Bit 8)                                          */
#define GPIO_DATA_IN_DIN8_Msk             (0x100UL)                 /*!< DIN8 (Bitfield-Mask: 0x01)                            */
#define GPIO_DATA_IN_DIN7_Pos             (7UL)                     /*!< DIN7 (Bit 7)                                          */
#define GPIO_DATA_IN_DIN7_Msk             (0x80UL)                  /*!< DIN7 (Bitfield-Mask: 0x01)                            */
#define GPIO_DATA_IN_DIN6_Pos             (6UL)                     /*!< DIN6 (Bit 6)                                          */
#define GPIO_DATA_IN_DIN6_Msk             (0x40UL)                  /*!< DIN6 (Bitfield-Mask: 0x01)                            */
#define GPIO_DATA_IN_DIN5_Pos             (5UL)                     /*!< DIN5 (Bit 5)                                          */
#define GPIO_DATA_IN_DIN5_Msk             (0x20UL)                  /*!< DIN5 (Bitfield-Mask: 0x01)                            */
#define GPIO_DATA_IN_DIN4_Pos             (4UL)                     /*!< DIN4 (Bit 4)                                          */
#define GPIO_DATA_IN_DIN4_Msk             (0x10UL)                  /*!< DIN4 (Bitfield-Mask: 0x01)                            */
#define GPIO_DATA_IN_DIN3_Pos             (3UL)                     /*!< DIN3 (Bit 3)                                          */
#define GPIO_DATA_IN_DIN3_Msk             (0x8UL)                   /*!< DIN3 (Bitfield-Mask: 0x01)                            */
#define GPIO_DATA_IN_DIN2_Pos             (2UL)                     /*!< DIN2 (Bit 2)                                          */
#define GPIO_DATA_IN_DIN2_Msk             (0x4UL)                   /*!< DIN2 (Bitfield-Mask: 0x01)                            */
#define GPIO_DATA_IN_DIN1_Pos             (1UL)                     /*!< DIN1 (Bit 1)                                          */
#define GPIO_DATA_IN_DIN1_Msk             (0x2UL)                   /*!< DIN1 (Bitfield-Mask: 0x01)                            */
#define GPIO_DATA_IN_DIN0_Pos             (0UL)                     /*!< DIN0 (Bit 0)                                          */
#define GPIO_DATA_IN_DIN0_Msk             (0x1UL)                   /*!< DIN0 (Bitfield-Mask: 0x01)                            */
/* =======================================================  DATA_OUT  ======================================================== */
#define GPIO_DATA_OUT_DOUT15_Pos          (15UL)                    /*!< DOUT15 (Bit 15)                                       */
#define GPIO_DATA_OUT_DOUT15_Msk          (0x8000UL)                /*!< DOUT15 (Bitfield-Mask: 0x01)                          */
#define GPIO_DATA_OUT_DOUT14_Pos          (14UL)                    /*!< DOUT14 (Bit 14)                                       */
#define GPIO_DATA_OUT_DOUT14_Msk          (0x4000UL)                /*!< DOUT14 (Bitfield-Mask: 0x01)                          */
#define GPIO_DATA_OUT_DOUT13_Pos          (13UL)                    /*!< DOUT13 (Bit 13)                                       */
#define GPIO_DATA_OUT_DOUT13_Msk          (0x2000UL)                /*!< DOUT13 (Bitfield-Mask: 0x01)                          */
#define GPIO_DATA_OUT_DOUT12_Pos          (12UL)                    /*!< DOUT12 (Bit 12)                                       */
#define GPIO_DATA_OUT_DOUT12_Msk          (0x1000UL)                /*!< DOUT12 (Bitfield-Mask: 0x01)                          */
#define GPIO_DATA_OUT_DOUT11_Pos          (11UL)                    /*!< DOUT11 (Bit 11)                                       */
#define GPIO_DATA_OUT_DOUT11_Msk          (0x800UL)                 /*!< DOUT11 (Bitfield-Mask: 0x01)                          */
#define GPIO_DATA_OUT_DOUT10_Pos          (10UL)                    /*!< DOUT10 (Bit 10)                                       */
#define GPIO_DATA_OUT_DOUT10_Msk          (0x400UL)                 /*!< DOUT10 (Bitfield-Mask: 0x01)                          */
#define GPIO_DATA_OUT_DOUT9_Pos           (9UL)                     /*!< DOUT9 (Bit 9)                                         */
#define GPIO_DATA_OUT_DOUT9_Msk           (0x200UL)                 /*!< DOUT9 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_OUT_DOUT8_Pos           (8UL)                     /*!< DOUT8 (Bit 8)                                         */
#define GPIO_DATA_OUT_DOUT8_Msk           (0x100UL)                 /*!< DOUT8 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_OUT_DOUT7_Pos           (7UL)                     /*!< DOUT7 (Bit 7)                                         */
#define GPIO_DATA_OUT_DOUT7_Msk           (0x80UL)                  /*!< DOUT7 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_OUT_DOUT6_Pos           (6UL)                     /*!< DOUT6 (Bit 6)                                         */
#define GPIO_DATA_OUT_DOUT6_Msk           (0x40UL)                  /*!< DOUT6 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_OUT_DOUT5_Pos           (5UL)                     /*!< DOUT5 (Bit 5)                                         */
#define GPIO_DATA_OUT_DOUT5_Msk           (0x20UL)                  /*!< DOUT5 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_OUT_DOUT4_Pos           (4UL)                     /*!< DOUT4 (Bit 4)                                         */
#define GPIO_DATA_OUT_DOUT4_Msk           (0x10UL)                  /*!< DOUT4 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_OUT_DOUT3_Pos           (3UL)                     /*!< DOUT3 (Bit 3)                                         */
#define GPIO_DATA_OUT_DOUT3_Msk           (0x8UL)                   /*!< DOUT3 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_OUT_DOUT2_Pos           (2UL)                     /*!< DOUT2 (Bit 2)                                         */
#define GPIO_DATA_OUT_DOUT2_Msk           (0x4UL)                   /*!< DOUT2 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_OUT_DOUT1_Pos           (1UL)                     /*!< DOUT1 (Bit 1)                                         */
#define GPIO_DATA_OUT_DOUT1_Msk           (0x2UL)                   /*!< DOUT1 (Bitfield-Mask: 0x01)                           */
#define GPIO_DATA_OUT_DOUT0_Pos           (0UL)                     /*!< DOUT0 (Bit 0)                                         */
#define GPIO_DATA_OUT_DOUT0_Msk           (0x1UL)                   /*!< DOUT0 (Bitfield-Mask: 0x01)                           */
/* ======================================================  BIT_SET_RST  ====================================================== */
#define GPIO_BIT_SET_RST_RST15_Pos        (31UL)                    /*!< RST15 (Bit 31)                                        */
#define GPIO_BIT_SET_RST_RST15_Msk        (0x80000000UL)            /*!< RST15 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_RST14_Pos        (30UL)                    /*!< RST14 (Bit 30)                                        */
#define GPIO_BIT_SET_RST_RST14_Msk        (0x40000000UL)            /*!< RST14 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_RST13_Pos        (29UL)                    /*!< RST13 (Bit 29)                                        */
#define GPIO_BIT_SET_RST_RST13_Msk        (0x20000000UL)            /*!< RST13 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_RST12_Pos        (28UL)                    /*!< RST12 (Bit 28)                                        */
#define GPIO_BIT_SET_RST_RST12_Msk        (0x10000000UL)            /*!< RST12 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_RST11_Pos        (27UL)                    /*!< RST11 (Bit 27)                                        */
#define GPIO_BIT_SET_RST_RST11_Msk        (0x8000000UL)             /*!< RST11 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_RST10_Pos        (26UL)                    /*!< RST10 (Bit 26)                                        */
#define GPIO_BIT_SET_RST_RST10_Msk        (0x4000000UL)             /*!< RST10 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_RST9_Pos         (25UL)                    /*!< RST9 (Bit 25)                                         */
#define GPIO_BIT_SET_RST_RST9_Msk         (0x2000000UL)             /*!< RST9 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_RST8_Pos         (24UL)                    /*!< RST8 (Bit 24)                                         */
#define GPIO_BIT_SET_RST_RST8_Msk         (0x1000000UL)             /*!< RST8 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_RST7_Pos         (23UL)                    /*!< RST7 (Bit 23)                                         */
#define GPIO_BIT_SET_RST_RST7_Msk         (0x800000UL)              /*!< RST7 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_RST6_Pos         (22UL)                    /*!< RST6 (Bit 22)                                         */
#define GPIO_BIT_SET_RST_RST6_Msk         (0x400000UL)              /*!< RST6 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_RST5_Pos         (21UL)                    /*!< RST5 (Bit 21)                                         */
#define GPIO_BIT_SET_RST_RST5_Msk         (0x200000UL)              /*!< RST5 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_RST4_Pos         (20UL)                    /*!< RST4 (Bit 20)                                         */
#define GPIO_BIT_SET_RST_RST4_Msk         (0x100000UL)              /*!< RST4 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_RST3_Pos         (19UL)                    /*!< RST3 (Bit 19)                                         */
#define GPIO_BIT_SET_RST_RST3_Msk         (0x80000UL)               /*!< RST3 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_RST2_Pos         (18UL)                    /*!< RST2 (Bit 18)                                         */
#define GPIO_BIT_SET_RST_RST2_Msk         (0x40000UL)               /*!< RST2 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_RST1_Pos         (17UL)                    /*!< RST1 (Bit 17)                                         */
#define GPIO_BIT_SET_RST_RST1_Msk         (0x20000UL)               /*!< RST1 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_RST0_Pos         (16UL)                    /*!< RST0 (Bit 16)                                         */
#define GPIO_BIT_SET_RST_RST0_Msk         (0x10000UL)               /*!< RST0 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET15_Pos        (15UL)                    /*!< SET15 (Bit 15)                                        */
#define GPIO_BIT_SET_RST_SET15_Msk        (0x8000UL)                /*!< SET15 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_SET14_Pos        (14UL)                    /*!< SET14 (Bit 14)                                        */
#define GPIO_BIT_SET_RST_SET14_Msk        (0x4000UL)                /*!< SET14 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_SET13_Pos        (13UL)                    /*!< SET13 (Bit 13)                                        */
#define GPIO_BIT_SET_RST_SET13_Msk        (0x2000UL)                /*!< SET13 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_SET12_Pos        (12UL)                    /*!< SET12 (Bit 12)                                        */
#define GPIO_BIT_SET_RST_SET12_Msk        (0x1000UL)                /*!< SET12 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_SET11_Pos        (11UL)                    /*!< SET11 (Bit 11)                                        */
#define GPIO_BIT_SET_RST_SET11_Msk        (0x800UL)                 /*!< SET11 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_SET10_Pos        (10UL)                    /*!< SET10 (Bit 10)                                        */
#define GPIO_BIT_SET_RST_SET10_Msk        (0x400UL)                 /*!< SET10 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_SET_RST_SET9_Pos         (9UL)                     /*!< SET9 (Bit 9)                                          */
#define GPIO_BIT_SET_RST_SET9_Msk         (0x200UL)                 /*!< SET9 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET8_Pos         (8UL)                     /*!< SET8 (Bit 8)                                          */
#define GPIO_BIT_SET_RST_SET8_Msk         (0x100UL)                 /*!< SET8 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET7_Pos         (7UL)                     /*!< SET7 (Bit 7)                                          */
#define GPIO_BIT_SET_RST_SET7_Msk         (0x80UL)                  /*!< SET7 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET6_Pos         (6UL)                     /*!< SET6 (Bit 6)                                          */
#define GPIO_BIT_SET_RST_SET6_Msk         (0x40UL)                  /*!< SET6 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET5_Pos         (5UL)                     /*!< SET5 (Bit 5)                                          */
#define GPIO_BIT_SET_RST_SET5_Msk         (0x20UL)                  /*!< SET5 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET4_Pos         (4UL)                     /*!< SET4 (Bit 4)                                          */
#define GPIO_BIT_SET_RST_SET4_Msk         (0x10UL)                  /*!< SET4 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET3_Pos         (3UL)                     /*!< SET3 (Bit 3)                                          */
#define GPIO_BIT_SET_RST_SET3_Msk         (0x8UL)                   /*!< SET3 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET2_Pos         (2UL)                     /*!< SET2 (Bit 2)                                          */
#define GPIO_BIT_SET_RST_SET2_Msk         (0x4UL)                   /*!< SET2 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET1_Pos         (1UL)                     /*!< SET1 (Bit 1)                                          */
#define GPIO_BIT_SET_RST_SET1_Msk         (0x2UL)                   /*!< SET1 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_SET_RST_SET0_Pos         (0UL)                     /*!< SET0 (Bit 0)                                          */
#define GPIO_BIT_SET_RST_SET0_Msk         (0x1UL)                   /*!< SET0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  BIT_RST  ======================================================== */
#define GPIO_BIT_RST_RST15_Pos            (15UL)                    /*!< RST15 (Bit 15)                                        */
#define GPIO_BIT_RST_RST15_Msk            (0x8000UL)                /*!< RST15 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_RST_RST14_Pos            (14UL)                    /*!< RST14 (Bit 14)                                        */
#define GPIO_BIT_RST_RST14_Msk            (0x4000UL)                /*!< RST14 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_RST_RST13_Pos            (13UL)                    /*!< RST13 (Bit 13)                                        */
#define GPIO_BIT_RST_RST13_Msk            (0x2000UL)                /*!< RST13 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_RST_RST12_Pos            (12UL)                    /*!< RST12 (Bit 12)                                        */
#define GPIO_BIT_RST_RST12_Msk            (0x1000UL)                /*!< RST12 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_RST_RST11_Pos            (11UL)                    /*!< RST11 (Bit 11)                                        */
#define GPIO_BIT_RST_RST11_Msk            (0x800UL)                 /*!< RST11 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_RST_RST10_Pos            (10UL)                    /*!< RST10 (Bit 10)                                        */
#define GPIO_BIT_RST_RST10_Msk            (0x400UL)                 /*!< RST10 (Bitfield-Mask: 0x01)                           */
#define GPIO_BIT_RST_RST9_Pos             (9UL)                     /*!< RST9 (Bit 9)                                          */
#define GPIO_BIT_RST_RST9_Msk             (0x200UL)                 /*!< RST9 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_RST_RST8_Pos             (8UL)                     /*!< RST8 (Bit 8)                                          */
#define GPIO_BIT_RST_RST8_Msk             (0x100UL)                 /*!< RST8 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_RST_RST7_Pos             (7UL)                     /*!< RST7 (Bit 7)                                          */
#define GPIO_BIT_RST_RST7_Msk             (0x80UL)                  /*!< RST7 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_RST_RST6_Pos             (6UL)                     /*!< RST6 (Bit 6)                                          */
#define GPIO_BIT_RST_RST6_Msk             (0x40UL)                  /*!< RST6 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_RST_RST5_Pos             (5UL)                     /*!< RST5 (Bit 5)                                          */
#define GPIO_BIT_RST_RST5_Msk             (0x20UL)                  /*!< RST5 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_RST_RST4_Pos             (4UL)                     /*!< RST4 (Bit 4)                                          */
#define GPIO_BIT_RST_RST4_Msk             (0x10UL)                  /*!< RST4 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_RST_RST3_Pos             (3UL)                     /*!< RST3 (Bit 3)                                          */
#define GPIO_BIT_RST_RST3_Msk             (0x8UL)                   /*!< RST3 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_RST_RST2_Pos             (2UL)                     /*!< RST2 (Bit 2)                                          */
#define GPIO_BIT_RST_RST2_Msk             (0x4UL)                   /*!< RST2 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_RST_RST1_Pos             (1UL)                     /*!< RST1 (Bit 1)                                          */
#define GPIO_BIT_RST_RST1_Msk             (0x2UL)                   /*!< RST1 (Bitfield-Mask: 0x01)                            */
#define GPIO_BIT_RST_RST0_Pos             (0UL)                     /*!< RST0 (Bit 0)                                          */
#define GPIO_BIT_RST_RST0_Msk             (0x1UL)                   /*!< RST0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  LOCK  ========================================================== */
#define GPIO_LOCK_KEY_Pos                 (16UL)                    /*!< KEY (Bit 16)                                          */
#define GPIO_LOCK_KEY_Msk                 (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define GPIO_LOCK_LK_Pos                  (0UL)                     /*!< LK (Bit 0)                                            */
#define GPIO_LOCK_LK_Msk                  (0x1UL)                   /*!< LK (Bitfield-Mask: 0x01)                              */
/* ========================================================  AF_LOW  ========================================================= */
#define GPIO_AF_LOW_AFSEL7_Pos            (28UL)                    /*!< AFSEL7 (Bit 28)                                       */
#define GPIO_AF_LOW_AFSEL7_Msk            (0xf0000000UL)            /*!< AFSEL7 (Bitfield-Mask: 0x0f)                          */
#define GPIO_AF_LOW_AFSEL6_Pos            (24UL)                    /*!< AFSEL6 (Bit 24)                                       */
#define GPIO_AF_LOW_AFSEL6_Msk            (0xf000000UL)             /*!< AFSEL6 (Bitfield-Mask: 0x0f)                          */
#define GPIO_AF_LOW_AFSEL5_Pos            (20UL)                    /*!< AFSEL5 (Bit 20)                                       */
#define GPIO_AF_LOW_AFSEL5_Msk            (0xf00000UL)              /*!< AFSEL5 (Bitfield-Mask: 0x0f)                          */
#define GPIO_AF_LOW_AFSEL4_Pos            (16UL)                    /*!< AFSEL4 (Bit 16)                                       */
#define GPIO_AF_LOW_AFSEL4_Msk            (0xf0000UL)               /*!< AFSEL4 (Bitfield-Mask: 0x0f)                          */
#define GPIO_AF_LOW_AFSEL3_Pos            (12UL)                    /*!< AFSEL3 (Bit 12)                                       */
#define GPIO_AF_LOW_AFSEL3_Msk            (0xf000UL)                /*!< AFSEL3 (Bitfield-Mask: 0x0f)                          */
#define GPIO_AF_LOW_AFSEL2_Pos            (8UL)                     /*!< AFSEL2 (Bit 8)                                        */
#define GPIO_AF_LOW_AFSEL2_Msk            (0xf00UL)                 /*!< AFSEL2 (Bitfield-Mask: 0x0f)                          */
#define GPIO_AF_LOW_AFSEL1_Pos            (4UL)                     /*!< AFSEL1 (Bit 4)                                        */
#define GPIO_AF_LOW_AFSEL1_Msk            (0xf0UL)                  /*!< AFSEL1 (Bitfield-Mask: 0x0f)                          */
#define GPIO_AF_LOW_AFSEL0_Pos            (0UL)                     /*!< AFSEL0 (Bit 0)                                        */
#define GPIO_AF_LOW_AFSEL0_Msk            (0xfUL)                   /*!< AFSEL0 (Bitfield-Mask: 0x0f)                          */
/* ========================================================  AF_HIGH  ======================================================== */
#define GPIO_AF_HIGH_AFSEL15_Pos          (28UL)                    /*!< AFSEL15 (Bit 28)                                      */
#define GPIO_AF_HIGH_AFSEL15_Msk          (0xf0000000UL)            /*!< AFSEL15 (Bitfield-Mask: 0x0f)                         */
#define GPIO_AF_HIGH_AFSEL14_Pos          (24UL)                    /*!< AFSEL14 (Bit 24)                                      */
#define GPIO_AF_HIGH_AFSEL14_Msk          (0xf000000UL)             /*!< AFSEL14 (Bitfield-Mask: 0x0f)                         */
#define GPIO_AF_HIGH_AFSEL13_Pos          (20UL)                    /*!< AFSEL13 (Bit 20)                                      */
#define GPIO_AF_HIGH_AFSEL13_Msk          (0xf00000UL)              /*!< AFSEL13 (Bitfield-Mask: 0x0f)                         */
#define GPIO_AF_HIGH_AFSEL12_Pos          (16UL)                    /*!< AFSEL12 (Bit 16)                                      */
#define GPIO_AF_HIGH_AFSEL12_Msk          (0xf0000UL)               /*!< AFSEL12 (Bitfield-Mask: 0x0f)                         */
#define GPIO_AF_HIGH_AFSEL11_Pos          (12UL)                    /*!< AFSEL11 (Bit 12)                                      */
#define GPIO_AF_HIGH_AFSEL11_Msk          (0xf000UL)                /*!< AFSEL11 (Bitfield-Mask: 0x0f)                         */
#define GPIO_AF_HIGH_AFSEL10_Pos          (8UL)                     /*!< AFSEL10 (Bit 8)                                       */
#define GPIO_AF_HIGH_AFSEL10_Msk          (0xf00UL)                 /*!< AFSEL10 (Bitfield-Mask: 0x0f)                         */
#define GPIO_AF_HIGH_AFSEL9_Pos           (4UL)                     /*!< AFSEL9 (Bit 4)                                        */
#define GPIO_AF_HIGH_AFSEL9_Msk           (0xf0UL)                  /*!< AFSEL9 (Bitfield-Mask: 0x0f)                          */
#define GPIO_AF_HIGH_AFSEL8_Pos           (0UL)                     /*!< AFSEL8 (Bit 0)                                        */
#define GPIO_AF_HIGH_AFSEL8_Msk           (0xfUL)                   /*!< AFSEL8 (Bitfield-Mask: 0x0f)                          */
/* ========================================================  ANA_AF  ========================================================= */
#define GPIO_ANA_AF_ANA_AFSEL15_Pos       (30UL)                    /*!< ANA_AFSEL15 (Bit 30)                                  */
#define GPIO_ANA_AF_ANA_AFSEL15_Msk       (0xc0000000UL)            /*!< ANA_AFSEL15 (Bitfield-Mask: 0x03)                     */
#define GPIO_ANA_AF_ANA_AFSEL14_Pos       (28UL)                    /*!< ANA_AFSEL14 (Bit 28)                                  */
#define GPIO_ANA_AF_ANA_AFSEL14_Msk       (0x30000000UL)            /*!< ANA_AFSEL14 (Bitfield-Mask: 0x03)                     */
#define GPIO_ANA_AF_ANA_AFSEL13_Pos       (26UL)                    /*!< ANA_AFSEL13 (Bit 26)                                  */
#define GPIO_ANA_AF_ANA_AFSEL13_Msk       (0xc000000UL)             /*!< ANA_AFSEL13 (Bitfield-Mask: 0x03)                     */
#define GPIO_ANA_AF_ANA_AFSEL12_Pos       (24UL)                    /*!< ANA_AFSEL12 (Bit 24)                                  */
#define GPIO_ANA_AF_ANA_AFSEL12_Msk       (0x3000000UL)             /*!< ANA_AFSEL12 (Bitfield-Mask: 0x03)                     */
#define GPIO_ANA_AF_ANA_AFSEL11_Pos       (22UL)                    /*!< ANA_AFSEL11 (Bit 22)                                  */
#define GPIO_ANA_AF_ANA_AFSEL11_Msk       (0xc00000UL)              /*!< ANA_AFSEL11 (Bitfield-Mask: 0x03)                     */
#define GPIO_ANA_AF_ANA_AFSEL10_Pos       (20UL)                    /*!< ANA_AFSEL10 (Bit 20)                                  */
#define GPIO_ANA_AF_ANA_AFSEL10_Msk       (0x300000UL)              /*!< ANA_AFSEL10 (Bitfield-Mask: 0x03)                     */
#define GPIO_ANA_AF_ANA_AFSEL9_Pos        (18UL)                    /*!< ANA_AFSEL9 (Bit 18)                                   */
#define GPIO_ANA_AF_ANA_AFSEL9_Msk        (0xc0000UL)               /*!< ANA_AFSEL9 (Bitfield-Mask: 0x03)                      */
#define GPIO_ANA_AF_ANA_AFSEL8_Pos        (16UL)                    /*!< ANA_AFSEL8 (Bit 16)                                   */
#define GPIO_ANA_AF_ANA_AFSEL8_Msk        (0x30000UL)               /*!< ANA_AFSEL8 (Bitfield-Mask: 0x03)                      */
#define GPIO_ANA_AF_ANA_AFSEL7_Pos        (14UL)                    /*!< ANA_AFSEL7 (Bit 14)                                   */
#define GPIO_ANA_AF_ANA_AFSEL7_Msk        (0xc000UL)                /*!< ANA_AFSEL7 (Bitfield-Mask: 0x03)                      */
#define GPIO_ANA_AF_ANA_AFSEL6_Pos        (12UL)                    /*!< ANA_AFSEL6 (Bit 12)                                   */
#define GPIO_ANA_AF_ANA_AFSEL6_Msk        (0x3000UL)                /*!< ANA_AFSEL6 (Bitfield-Mask: 0x03)                      */
#define GPIO_ANA_AF_ANA_AFSEL5_Pos        (10UL)                    /*!< ANA_AFSEL5 (Bit 10)                                   */
#define GPIO_ANA_AF_ANA_AFSEL5_Msk        (0xc00UL)                 /*!< ANA_AFSEL5 (Bitfield-Mask: 0x03)                      */
#define GPIO_ANA_AF_ANA_AFSEL4_Pos        (8UL)                     /*!< ANA_AFSEL4 (Bit 8)                                    */
#define GPIO_ANA_AF_ANA_AFSEL4_Msk        (0x300UL)                 /*!< ANA_AFSEL4 (Bitfield-Mask: 0x03)                      */
#define GPIO_ANA_AF_ANA_AFSEL3_Pos        (6UL)                     /*!< ANA_AFSEL3 (Bit 6)                                    */
#define GPIO_ANA_AF_ANA_AFSEL3_Msk        (0xc0UL)                  /*!< ANA_AFSEL3 (Bitfield-Mask: 0x03)                      */
#define GPIO_ANA_AF_ANA_AFSEL2_Pos        (4UL)                     /*!< ANA_AFSEL2 (Bit 4)                                    */
#define GPIO_ANA_AF_ANA_AFSEL2_Msk        (0x30UL)                  /*!< ANA_AFSEL2 (Bitfield-Mask: 0x03)                      */
#define GPIO_ANA_AF_ANA_AFSEL1_Pos        (2UL)                     /*!< ANA_AFSEL1 (Bit 2)                                    */
#define GPIO_ANA_AF_ANA_AFSEL1_Msk        (0xcUL)                   /*!< ANA_AFSEL1 (Bitfield-Mask: 0x03)                      */
#define GPIO_ANA_AF_ANA_AFSEL0_Pos        (0UL)                     /*!< ANA_AFSEL0 (Bit 0)                                    */
#define GPIO_ANA_AF_ANA_AFSEL0_Msk        (0x3UL)                   /*!< ANA_AFSEL0 (Bitfield-Mask: 0x03)                      */
/* ========================================================  INT_EN  ========================================================= */
#define GPIO_INT_EN_IE15_Pos              (15UL)                    /*!< IE15 (Bit 15)                                         */
#define GPIO_INT_EN_IE15_Msk              (0x8000UL)                /*!< IE15 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_EN_IE14_Pos              (14UL)                    /*!< IE14 (Bit 14)                                         */
#define GPIO_INT_EN_IE14_Msk              (0x4000UL)                /*!< IE14 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_EN_IE13_Pos              (13UL)                    /*!< IE13 (Bit 13)                                         */
#define GPIO_INT_EN_IE13_Msk              (0x2000UL)                /*!< IE13 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_EN_IE12_Pos              (12UL)                    /*!< IE12 (Bit 12)                                         */
#define GPIO_INT_EN_IE12_Msk              (0x1000UL)                /*!< IE12 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_EN_IE11_Pos              (11UL)                    /*!< IE11 (Bit 11)                                         */
#define GPIO_INT_EN_IE11_Msk              (0x800UL)                 /*!< IE11 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_EN_IE10_Pos              (10UL)                    /*!< IE10 (Bit 10)                                         */
#define GPIO_INT_EN_IE10_Msk              (0x400UL)                 /*!< IE10 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_EN_IE9_Pos               (9UL)                     /*!< IE9 (Bit 9)                                           */
#define GPIO_INT_EN_IE9_Msk               (0x200UL)                 /*!< IE9 (Bitfield-Mask: 0x01)                             */
#define GPIO_INT_EN_IE8_Pos               (8UL)                     /*!< IE8 (Bit 8)                                           */
#define GPIO_INT_EN_IE8_Msk               (0x100UL)                 /*!< IE8 (Bitfield-Mask: 0x01)                             */
#define GPIO_INT_EN_IE7_Pos               (7UL)                     /*!< IE7 (Bit 7)                                           */
#define GPIO_INT_EN_IE7_Msk               (0x80UL)                  /*!< IE7 (Bitfield-Mask: 0x01)                             */
#define GPIO_INT_EN_IE6_Pos               (6UL)                     /*!< IE6 (Bit 6)                                           */
#define GPIO_INT_EN_IE6_Msk               (0x40UL)                  /*!< IE6 (Bitfield-Mask: 0x01)                             */
#define GPIO_INT_EN_IE5_Pos               (5UL)                     /*!< IE5 (Bit 5)                                           */
#define GPIO_INT_EN_IE5_Msk               (0x20UL)                  /*!< IE5 (Bitfield-Mask: 0x01)                             */
#define GPIO_INT_EN_IE4_Pos               (4UL)                     /*!< IE4 (Bit 4)                                           */
#define GPIO_INT_EN_IE4_Msk               (0x10UL)                  /*!< IE4 (Bitfield-Mask: 0x01)                             */
#define GPIO_INT_EN_IE3_Pos               (3UL)                     /*!< IE3 (Bit 3)                                           */
#define GPIO_INT_EN_IE3_Msk               (0x8UL)                   /*!< IE3 (Bitfield-Mask: 0x01)                             */
#define GPIO_INT_EN_IE2_Pos               (2UL)                     /*!< IE2 (Bit 2)                                           */
#define GPIO_INT_EN_IE2_Msk               (0x4UL)                   /*!< IE2 (Bitfield-Mask: 0x01)                             */
#define GPIO_INT_EN_IE1_Pos               (1UL)                     /*!< IE1 (Bit 1)                                           */
#define GPIO_INT_EN_IE1_Msk               (0x2UL)                   /*!< IE1 (Bitfield-Mask: 0x01)                             */
#define GPIO_INT_EN_IE0_Pos               (0UL)                     /*!< IE0 (Bit 0)                                           */
#define GPIO_INT_EN_IE0_Msk               (0x1UL)                   /*!< IE0 (Bitfield-Mask: 0x01)                             */
/* =====================================================  INT_TYPE_LOW  ====================================================== */
#define GPIO_INT_TYPE_LOW_INT_TYPE7_Pos   (28UL)                    /*!< INT_TYPE7 (Bit 28)                                    */
#define GPIO_INT_TYPE_LOW_INT_TYPE7_Msk   (0x70000000UL)            /*!< INT_TYPE7 (Bitfield-Mask: 0x07)                       */
#define GPIO_INT_TYPE_LOW_INT_TYPE6_Pos   (24UL)                    /*!< INT_TYPE6 (Bit 24)                                    */
#define GPIO_INT_TYPE_LOW_INT_TYPE6_Msk   (0x7000000UL)             /*!< INT_TYPE6 (Bitfield-Mask: 0x07)                       */
#define GPIO_INT_TYPE_LOW_INT_TYPE5_Pos   (20UL)                    /*!< INT_TYPE5 (Bit 20)                                    */
#define GPIO_INT_TYPE_LOW_INT_TYPE5_Msk   (0x700000UL)              /*!< INT_TYPE5 (Bitfield-Mask: 0x07)                       */
#define GPIO_INT_TYPE_LOW_INT_TYPE4_Pos   (16UL)                    /*!< INT_TYPE4 (Bit 16)                                    */
#define GPIO_INT_TYPE_LOW_INT_TYPE4_Msk   (0x70000UL)               /*!< INT_TYPE4 (Bitfield-Mask: 0x07)                       */
#define GPIO_INT_TYPE_LOW_INT_TYPE3_Pos   (12UL)                    /*!< INT_TYPE3 (Bit 12)                                    */
#define GPIO_INT_TYPE_LOW_INT_TYPE3_Msk   (0x7000UL)                /*!< INT_TYPE3 (Bitfield-Mask: 0x07)                       */
#define GPIO_INT_TYPE_LOW_INT_TYPE2_Pos   (8UL)                     /*!< INT_TYPE2 (Bit 8)                                     */
#define GPIO_INT_TYPE_LOW_INT_TYPE2_Msk   (0x700UL)                 /*!< INT_TYPE2 (Bitfield-Mask: 0x07)                       */
#define GPIO_INT_TYPE_LOW_INT_TYPE1_Pos   (4UL)                     /*!< INT_TYPE1 (Bit 4)                                     */
#define GPIO_INT_TYPE_LOW_INT_TYPE1_Msk   (0x70UL)                  /*!< INT_TYPE1 (Bitfield-Mask: 0x07)                       */
#define GPIO_INT_TYPE_LOW_INT_TYPE0_Pos   (0UL)                     /*!< INT_TYPE0 (Bit 0)                                     */
#define GPIO_INT_TYPE_LOW_INT_TYPE0_Msk   (0x7UL)                   /*!< INT_TYPE0 (Bitfield-Mask: 0x07)                       */
/* =====================================================  INT_TYPE_HIGH  ===================================================== */
#define GPIO_INT_TYPE_HIGH_INT_TYPE15_Pos (28UL)                    /*!< INT_TYPE15 (Bit 28)                                   */
#define GPIO_INT_TYPE_HIGH_INT_TYPE15_Msk (0x70000000UL)            /*!< INT_TYPE15 (Bitfield-Mask: 0x07)                      */
#define GPIO_INT_TYPE_HIGH_INT_TYPE14_Pos (24UL)                    /*!< INT_TYPE14 (Bit 24)                                   */
#define GPIO_INT_TYPE_HIGH_INT_TYPE14_Msk (0x7000000UL)             /*!< INT_TYPE14 (Bitfield-Mask: 0x07)                      */
#define GPIO_INT_TYPE_HIGH_INT_TYPE13_Pos (20UL)                    /*!< INT_TYPE13 (Bit 20)                                   */
#define GPIO_INT_TYPE_HIGH_INT_TYPE13_Msk (0x700000UL)              /*!< INT_TYPE13 (Bitfield-Mask: 0x07)                      */
#define GPIO_INT_TYPE_HIGH_INT_TYPE12_Pos (16UL)                    /*!< INT_TYPE12 (Bit 16)                                   */
#define GPIO_INT_TYPE_HIGH_INT_TYPE12_Msk (0x70000UL)               /*!< INT_TYPE12 (Bitfield-Mask: 0x07)                      */
#define GPIO_INT_TYPE_HIGH_INT_TYPE11_Pos (12UL)                    /*!< INT_TYPE11 (Bit 12)                                   */
#define GPIO_INT_TYPE_HIGH_INT_TYPE11_Msk (0x7000UL)                /*!< INT_TYPE11 (Bitfield-Mask: 0x07)                      */
#define GPIO_INT_TYPE_HIGH_INT_TYPE10_Pos (8UL)                     /*!< INT_TYPE10 (Bit 8)                                    */
#define GPIO_INT_TYPE_HIGH_INT_TYPE10_Msk (0x700UL)                 /*!< INT_TYPE10 (Bitfield-Mask: 0x07)                      */
#define GPIO_INT_TYPE_HIGH_INT_TYPE9_Pos  (4UL)                     /*!< INT_TYPE9 (Bit 4)                                     */
#define GPIO_INT_TYPE_HIGH_INT_TYPE9_Msk  (0x70UL)                  /*!< INT_TYPE9 (Bitfield-Mask: 0x07)                       */
#define GPIO_INT_TYPE_HIGH_INT_TYPE8_Pos  (0UL)                     /*!< INT_TYPE8 (Bit 0)                                     */
#define GPIO_INT_TYPE_HIGH_INT_TYPE8_Msk  (0x7UL)                   /*!< INT_TYPE8 (Bitfield-Mask: 0x07)                       */
/* ========================================================  INT_SR  ========================================================= */
#define GPIO_INT_SR_INT15_Pos             (15UL)                    /*!< INT15 (Bit 15)                                        */
#define GPIO_INT_SR_INT15_Msk             (0x8000UL)                /*!< INT15 (Bitfield-Mask: 0x01)                           */
#define GPIO_INT_SR_INT14_Pos             (14UL)                    /*!< INT14 (Bit 14)                                        */
#define GPIO_INT_SR_INT14_Msk             (0x4000UL)                /*!< INT14 (Bitfield-Mask: 0x01)                           */
#define GPIO_INT_SR_INT13_Pos             (13UL)                    /*!< INT13 (Bit 13)                                        */
#define GPIO_INT_SR_INT13_Msk             (0x2000UL)                /*!< INT13 (Bitfield-Mask: 0x01)                           */
#define GPIO_INT_SR_INT12_Pos             (12UL)                    /*!< INT12 (Bit 12)                                        */
#define GPIO_INT_SR_INT12_Msk             (0x1000UL)                /*!< INT12 (Bitfield-Mask: 0x01)                           */
#define GPIO_INT_SR_INT11_Pos             (11UL)                    /*!< INT11 (Bit 11)                                        */
#define GPIO_INT_SR_INT11_Msk             (0x800UL)                 /*!< INT11 (Bitfield-Mask: 0x01)                           */
#define GPIO_INT_SR_INT10_Pos             (10UL)                    /*!< INT10 (Bit 10)                                        */
#define GPIO_INT_SR_INT10_Msk             (0x400UL)                 /*!< INT10 (Bitfield-Mask: 0x01)                           */
#define GPIO_INT_SR_INT9_Pos              (9UL)                     /*!< INT9 (Bit 9)                                          */
#define GPIO_INT_SR_INT9_Msk              (0x200UL)                 /*!< INT9 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_SR_INT8_Pos              (8UL)                     /*!< INT8 (Bit 8)                                          */
#define GPIO_INT_SR_INT8_Msk              (0x100UL)                 /*!< INT8 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_SR_INT7_Pos              (7UL)                     /*!< INT7 (Bit 7)                                          */
#define GPIO_INT_SR_INT7_Msk              (0x80UL)                  /*!< INT7 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_SR_INT6_Pos              (6UL)                     /*!< INT6 (Bit 6)                                          */
#define GPIO_INT_SR_INT6_Msk              (0x40UL)                  /*!< INT6 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_SR_INT5_Pos              (5UL)                     /*!< INT5 (Bit 5)                                          */
#define GPIO_INT_SR_INT5_Msk              (0x20UL)                  /*!< INT5 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_SR_INT4_Pos              (4UL)                     /*!< INT4 (Bit 4)                                          */
#define GPIO_INT_SR_INT4_Msk              (0x10UL)                  /*!< INT4 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_SR_INT3_Pos              (3UL)                     /*!< INT3 (Bit 3)                                          */
#define GPIO_INT_SR_INT3_Msk              (0x8UL)                   /*!< INT3 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_SR_INT2_Pos              (2UL)                     /*!< INT2 (Bit 2)                                          */
#define GPIO_INT_SR_INT2_Msk              (0x4UL)                   /*!< INT2 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_SR_INT1_Pos              (1UL)                     /*!< INT1 (Bit 1)                                          */
#define GPIO_INT_SR_INT1_Msk              (0x2UL)                   /*!< INT1 (Bitfield-Mask: 0x01)                            */
#define GPIO_INT_SR_INT0_Pos              (0UL)                     /*!< INT0 (Bit 0)                                          */
#define GPIO_INT_SR_INT0_Msk              (0x1UL)                   /*!< INT0 (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                           UART                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define UART_CR_HALF_DUP_Pos              (19UL)                    /*!< HALF_DUP (Bit 19)                                     */
#define UART_CR_HALF_DUP_Msk              (0x80000UL)               /*!< HALF_DUP (Bitfield-Mask: 0x01)                        */
#define UART_CR_MSB_FIRST_Pos             (18UL)                    /*!< MSB_FIRST (Bit 18)                                    */
#define UART_CR_MSB_FIRST_Msk             (0x40000UL)               /*!< MSB_FIRST (Bitfield-Mask: 0x01)                       */
#define UART_CR_TX_DMAEN_Pos              (17UL)                    /*!< TX_DMAEN (Bit 17)                                     */
#define UART_CR_TX_DMAEN_Msk              (0x20000UL)               /*!< TX_DMAEN (Bitfield-Mask: 0x01)                        */
#define UART_CR_RX_DMAEN_Pos              (16UL)                    /*!< RX_DMAEN (Bit 16)                                     */
#define UART_CR_RX_DMAEN_Msk              (0x10000UL)               /*!< RX_DMAEN (Bitfield-Mask: 0x01)                        */
#define UART_CR_IDLE_IE_Pos               (12UL)                    /*!< IDLE_IE (Bit 12)                                      */
#define UART_CR_IDLE_IE_Msk               (0x1000UL)                /*!< IDLE_IE (Bitfield-Mask: 0x01)                         */
#define UART_CR_ERR_IE_Pos                (11UL)                    /*!< ERR_IE (Bit 11)                                       */
#define UART_CR_ERR_IE_Msk                (0x800UL)                 /*!< ERR_IE (Bitfield-Mask: 0x01)                          */
#define UART_CR_TXE_IE_Pos                (10UL)                    /*!< TXE_IE (Bit 10)                                       */
#define UART_CR_TXE_IE_Msk                (0x400UL)                 /*!< TXE_IE (Bitfield-Mask: 0x01)                          */
#define UART_CR_TXC_IE_Pos                (9UL)                     /*!< TXC_IE (Bit 9)                                        */
#define UART_CR_TXC_IE_Msk                (0x200UL)                 /*!< TXC_IE (Bitfield-Mask: 0x01)                          */
#define UART_CR_RXNE_IE_Pos               (8UL)                     /*!< RXNE_IE (Bit 8)                                       */
#define UART_CR_RXNE_IE_Msk               (0x100UL)                 /*!< RXNE_IE (Bitfield-Mask: 0x01)                         */
#define UART_CR_PARITY_SEL_Pos            (7UL)                     /*!< PARITY_SEL (Bit 7)                                    */
#define UART_CR_PARITY_SEL_Msk            (0x80UL)                  /*!< PARITY_SEL (Bitfield-Mask: 0x01)                      */
#define UART_CR_PARITY_EN_Pos             (6UL)                     /*!< PARITY_EN (Bit 6)                                     */
#define UART_CR_PARITY_EN_Msk             (0x40UL)                  /*!< PARITY_EN (Bitfield-Mask: 0x01)                       */
#define UART_CR_STOP_LEN_Pos              (5UL)                     /*!< STOP_LEN (Bit 5)                                      */
#define UART_CR_STOP_LEN_Msk              (0x20UL)                  /*!< STOP_LEN (Bitfield-Mask: 0x01)                        */
#define UART_CR_DATA_LEN_Pos              (3UL)                     /*!< DATA_LEN (Bit 3)                                      */
#define UART_CR_DATA_LEN_Msk              (0x18UL)                  /*!< DATA_LEN (Bitfield-Mask: 0x03)                        */
#define UART_CR_TX_EN_Pos                 (2UL)                     /*!< TX_EN (Bit 2)                                         */
#define UART_CR_TX_EN_Msk                 (0x4UL)                   /*!< TX_EN (Bitfield-Mask: 0x01)                           */
#define UART_CR_RX_EN_Pos                 (1UL)                     /*!< RX_EN (Bit 1)                                         */
#define UART_CR_RX_EN_Msk                 (0x2UL)                   /*!< RX_EN (Bitfield-Mask: 0x01)                           */
#define UART_CR_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define UART_CR_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ISR  ========================================================== */
#define UART_ISR_IDLE_Pos                 (6UL)                     /*!< IDLE (Bit 6)                                          */
#define UART_ISR_IDLE_Msk                 (0x40UL)                  /*!< IDLE (Bitfield-Mask: 0x01)                            */
#define UART_ISR_OVRR_ERR_Pos             (5UL)                     /*!< OVRR_ERR (Bit 5)                                      */
#define UART_ISR_OVRR_ERR_Msk             (0x20UL)                  /*!< OVRR_ERR (Bitfield-Mask: 0x01)                        */
#define UART_ISR_FRAME_ERR_Pos            (4UL)                     /*!< FRAME_ERR (Bit 4)                                     */
#define UART_ISR_FRAME_ERR_Msk            (0x10UL)                  /*!< FRAME_ERR (Bitfield-Mask: 0x01)                       */
#define UART_ISR_PARITY_ERR_Pos           (3UL)                     /*!< PARITY_ERR (Bit 3)                                    */
#define UART_ISR_PARITY_ERR_Msk           (0x8UL)                   /*!< PARITY_ERR (Bitfield-Mask: 0x01)                      */
#define UART_ISR_TXE_Pos                  (2UL)                     /*!< TXE (Bit 2)                                           */
#define UART_ISR_TXE_Msk                  (0x4UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
#define UART_ISR_TXC_Pos                  (1UL)                     /*!< TXC (Bit 1)                                           */
#define UART_ISR_TXC_Msk                  (0x2UL)                   /*!< TXC (Bitfield-Mask: 0x01)                             */
#define UART_ISR_RXNE_Pos                 (0UL)                     /*!< RXNE (Bit 0)                                          */
#define UART_ISR_RXNE_Msk                 (0x1UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
/* ==========================================================  BRR  ========================================================== */
#define UART_BRR_DIV_FRAC_Pos             (16UL)                    /*!< DIV_FRAC (Bit 16)                                     */
#define UART_BRR_DIV_FRAC_Msk             (0xf0000UL)               /*!< DIV_FRAC (Bitfield-Mask: 0x0f)                        */
#define UART_BRR_DIV_INT_Pos              (0UL)                     /*!< DIV_INT (Bit 0)                                       */
#define UART_BRR_DIV_INT_Msk              (0xffffUL)                /*!< DIV_INT (Bitfield-Mask: 0xffff)                       */
/* ==========================================================  TDR  ========================================================== */
#define UART_TDR_TDR_Pos                  (0UL)                     /*!< TDR (Bit 0)                                           */
#define UART_TDR_TDR_Msk                  (0x1ffUL)                 /*!< TDR (Bitfield-Mask: 0x1ff)                            */
/* ==========================================================  RDR  ========================================================== */
#define UART_RDR_RDR_Pos                  (0UL)                     /*!< RDR (Bit 0)                                           */
#define UART_RDR_RDR_Msk                  (0x1ffUL)                 /*!< RDR (Bitfield-Mask: 0x1ff)                            */


/* =========================================================================================================================== */
/* ================                                            RCC                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  COMMON_CR  ======================================================= */
#define RCC_COMMON_CR_LSE_ST_Pos          (30UL)                    /*!< LSE_ST (Bit 30)                                       */
#define RCC_COMMON_CR_LSE_ST_Msk          (0xc0000000UL)            /*!< LSE_ST (Bitfield-Mask: 0x03)                          */
#define RCC_COMMON_CR_HSE_ST_Pos          (28UL)                    /*!< HSE_ST (Bit 28)                                       */
#define RCC_COMMON_CR_HSE_ST_Msk          (0x30000000UL)            /*!< HSE_ST (Bitfield-Mask: 0x03)                          */
#define RCC_COMMON_CR_LSI_ST_Pos          (26UL)                    /*!< LSI_ST (Bit 26)                                       */
#define RCC_COMMON_CR_LSI_ST_Msk          (0xc000000UL)             /*!< LSI_ST (Bitfield-Mask: 0x03)                          */
#define RCC_COMMON_CR_HSI_ST_Pos          (24UL)                    /*!< HSI_ST (Bit 24)                                       */
#define RCC_COMMON_CR_HSI_ST_Msk          (0x3000000UL)             /*!< HSI_ST (Bitfield-Mask: 0x03)                          */
#define RCC_COMMON_CR_LSE_RDY_Pos         (23UL)                    /*!< LSE_RDY (Bit 23)                                      */
#define RCC_COMMON_CR_LSE_RDY_Msk         (0x800000UL)              /*!< LSE_RDY (Bitfield-Mask: 0x01)                         */
#define RCC_COMMON_CR_HSE_RDY_Pos         (22UL)                    /*!< HSE_RDY (Bit 22)                                      */
#define RCC_COMMON_CR_HSE_RDY_Msk         (0x400000UL)              /*!< HSE_RDY (Bitfield-Mask: 0x01)                         */
#define RCC_COMMON_CR_LSI_RDY_Pos         (21UL)                    /*!< LSI_RDY (Bit 21)                                      */
#define RCC_COMMON_CR_LSI_RDY_Msk         (0x200000UL)              /*!< LSI_RDY (Bitfield-Mask: 0x01)                         */
#define RCC_COMMON_CR_LSE_EN_Pos          (19UL)                    /*!< LSE_EN (Bit 19)                                       */
#define RCC_COMMON_CR_LSE_EN_Msk          (0x80000UL)               /*!< LSE_EN (Bitfield-Mask: 0x01)                          */
#define RCC_COMMON_CR_HSE_EN_Pos          (18UL)                    /*!< HSE_EN (Bit 18)                                       */
#define RCC_COMMON_CR_HSE_EN_Msk          (0x40000UL)               /*!< HSE_EN (Bitfield-Mask: 0x01)                          */
#define RCC_COMMON_CR_LSI_EN_Pos          (17UL)                    /*!< LSI_EN (Bit 17)                                       */
#define RCC_COMMON_CR_LSI_EN_Msk          (0x20000UL)               /*!< LSI_EN (Bitfield-Mask: 0x01)                          */
#define RCC_COMMON_CR_MCO_SEL_Pos         (13UL)                    /*!< MCO_SEL (Bit 13)                                      */
#define RCC_COMMON_CR_MCO_SEL_Msk         (0xe000UL)                /*!< MCO_SEL (Bitfield-Mask: 0x07)                         */
#define RCC_COMMON_CR_MCO_EN_Pos          (12UL)                    /*!< MCO_EN (Bit 12)                                       */
#define RCC_COMMON_CR_MCO_EN_Msk          (0x1000UL)                /*!< MCO_EN (Bitfield-Mask: 0x01)                          */
#define RCC_COMMON_CR_HSCK_SEL_Pos        (10UL)                    /*!< HSCK_SEL (Bit 10)                                     */
#define RCC_COMMON_CR_HSCK_SEL_Msk        (0x400UL)                 /*!< HSCK_SEL (Bitfield-Mask: 0x01)                        */
#define RCC_COMMON_CR_LSCK_SEL_Pos        (9UL)                     /*!< LSCK_SEL (Bit 9)                                      */
#define RCC_COMMON_CR_LSCK_SEL_Msk        (0x200UL)                 /*!< LSCK_SEL (Bitfield-Mask: 0x01)                        */
#define RCC_COMMON_CR_SYSCK_SEL_Pos       (8UL)                     /*!< SYSCK_SEL (Bit 8)                                     */
#define RCC_COMMON_CR_SYSCK_SEL_Msk       (0x100UL)                 /*!< SYSCK_SEL (Bitfield-Mask: 0x01)                       */
#define RCC_COMMON_CR_HCKD_Pos            (4UL)                     /*!< HCKD (Bit 4)                                          */
#define RCC_COMMON_CR_HCKD_Msk            (0x70UL)                  /*!< HCKD (Bitfield-Mask: 0x07)                            */
#define RCC_COMMON_CR_PCKD_Pos            (0UL)                     /*!< PCKD (Bit 0)                                          */
#define RCC_COMMON_CR_PCKD_Msk            (0x7UL)                   /*!< PCKD (Bitfield-Mask: 0x07)                            */
/* =======================================================  CLKEN_CR  ======================================================== */
#define RCC_CLKEN_CR_DSP_Pos              (25UL)                    /*!< DSP (Bit 25)                                          */
#define RCC_CLKEN_CR_DSP_Msk              (0x2000000UL)             /*!< DSP (Bitfield-Mask: 0x01)                             */
#define RCC_CLKEN_CR_GPIO_Pos             (24UL)                    /*!< GPIO (Bit 24)                                         */
#define RCC_CLKEN_CR_GPIO_Msk             (0x1000000UL)             /*!< GPIO (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_CRC_Pos              (22UL)                    /*!< CRC (Bit 22)                                          */
#define RCC_CLKEN_CR_CRC_Msk              (0x400000UL)              /*!< CRC (Bitfield-Mask: 0x01)                             */
#define RCC_CLKEN_CR_DMA_Pos              (21UL)                    /*!< DMA (Bit 21)                                          */
#define RCC_CLKEN_CR_DMA_Msk              (0x200000UL)              /*!< DMA (Bitfield-Mask: 0x01)                             */
#define RCC_CLKEN_CR_TIM5_Pos             (20UL)                    /*!< TIM5 (Bit 20)                                         */
#define RCC_CLKEN_CR_TIM5_Msk             (0x100000UL)              /*!< TIM5 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_TIM4_Pos             (19UL)                    /*!< TIM4 (Bit 19)                                         */
#define RCC_CLKEN_CR_TIM4_Msk             (0x80000UL)               /*!< TIM4 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_ACMP_Pos             (18UL)                    /*!< ACMP (Bit 18)                                         */
#define RCC_CLKEN_CR_ACMP_Msk             (0x40000UL)               /*!< ACMP (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_CAN_Pos              (17UL)                    /*!< CAN (Bit 17)                                          */
#define RCC_CLKEN_CR_CAN_Msk              (0x20000UL)               /*!< CAN (Bitfield-Mask: 0x01)                             */
#define RCC_CLKEN_CR_POSIF_Pos            (16UL)                    /*!< POSIF (Bit 16)                                        */
#define RCC_CLKEN_CR_POSIF_Msk            (0x10000UL)               /*!< POSIF (Bitfield-Mask: 0x01)                           */
#define RCC_CLKEN_CR_I2C_Pos              (15UL)                    /*!< I2C (Bit 15)                                          */
#define RCC_CLKEN_CR_I2C_Msk              (0x8000UL)                /*!< I2C (Bitfield-Mask: 0x01)                             */
#define RCC_CLKEN_CR_DAC_Pos              (14UL)                    /*!< DAC (Bit 14)                                          */
#define RCC_CLKEN_CR_DAC_Msk              (0x4000UL)                /*!< DAC (Bitfield-Mask: 0x01)                             */
#define RCC_CLKEN_CR_ADC_Pos              (13UL)                    /*!< ADC (Bit 13)                                          */
#define RCC_CLKEN_CR_ADC_Msk              (0x2000UL)                /*!< ADC (Bitfield-Mask: 0x01)                             */
#define RCC_CLKEN_CR_PVD_Pos              (12UL)                    /*!< PVD (Bit 12)                                          */
#define RCC_CLKEN_CR_PVD_Msk              (0x1000UL)                /*!< PVD (Bitfield-Mask: 0x01)                             */
#define RCC_CLKEN_CR_EPWM_Pos             (11UL)                    /*!< EPWM (Bit 11)                                         */
#define RCC_CLKEN_CR_EPWM_Msk             (0x800UL)                 /*!< EPWM (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_CCT1_Pos             (10UL)                    /*!< CCT1 (Bit 10)                                         */
#define RCC_CLKEN_CR_CCT1_Msk             (0x400UL)                 /*!< CCT1 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_CCT0_Pos             (9UL)                     /*!< CCT0 (Bit 9)                                          */
#define RCC_CLKEN_CR_CCT0_Msk             (0x200UL)                 /*!< CCT0 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_TIM3_Pos             (8UL)                     /*!< TIM3 (Bit 8)                                          */
#define RCC_CLKEN_CR_TIM3_Msk             (0x100UL)                 /*!< TIM3 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_TIM2_Pos             (7UL)                     /*!< TIM2 (Bit 7)                                          */
#define RCC_CLKEN_CR_TIM2_Msk             (0x80UL)                  /*!< TIM2 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_TIM1_Pos             (6UL)                     /*!< TIM1 (Bit 6)                                          */
#define RCC_CLKEN_CR_TIM1_Msk             (0x40UL)                  /*!< TIM1 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_TIM0_Pos             (5UL)                     /*!< TIM0 (Bit 5)                                          */
#define RCC_CLKEN_CR_TIM0_Msk             (0x20UL)                  /*!< TIM0 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_SPI1_Pos             (4UL)                     /*!< SPI1 (Bit 4)                                          */
#define RCC_CLKEN_CR_SPI1_Msk             (0x10UL)                  /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_SPI0_Pos             (3UL)                     /*!< SPI0 (Bit 3)                                          */
#define RCC_CLKEN_CR_SPI0_Msk             (0x8UL)                   /*!< SPI0 (Bitfield-Mask: 0x01)                            */
#define RCC_CLKEN_CR_UART2_Pos            (2UL)                     /*!< UART2 (Bit 2)                                         */
#define RCC_CLKEN_CR_UART2_Msk            (0x4UL)                   /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define RCC_CLKEN_CR_UART1_Pos            (1UL)                     /*!< UART1 (Bit 1)                                         */
#define RCC_CLKEN_CR_UART1_Msk            (0x2UL)                   /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define RCC_CLKEN_CR_UART0_Pos            (0UL)                     /*!< UART0 (Bit 0)                                         */
#define RCC_CLKEN_CR_UART0_Msk            (0x1UL)                   /*!< UART0 (Bitfield-Mask: 0x01)                           */
/* ========================================================  LPM_CR  ========================================================= */
#define RCC_LPM_CR_MODE_Pos               (0UL)                     /*!< MODE (Bit 0)                                          */
#define RCC_LPM_CR_MODE_Msk               (0x3UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
/* =====================================================  DEEP_SLEEP_CR  ===================================================== */
#define RCC_DEEP_SLEEP_CR_DSP_Pos         (25UL)                    /*!< DSP (Bit 25)                                          */
#define RCC_DEEP_SLEEP_CR_DSP_Msk         (0x2000000UL)             /*!< DSP (Bitfield-Mask: 0x01)                             */
#define RCC_DEEP_SLEEP_CR_GPIO_Pos        (24UL)                    /*!< GPIO (Bit 24)                                         */
#define RCC_DEEP_SLEEP_CR_GPIO_Msk        (0x1000000UL)             /*!< GPIO (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_CRC_Pos         (22UL)                    /*!< CRC (Bit 22)                                          */
#define RCC_DEEP_SLEEP_CR_CRC_Msk         (0x400000UL)              /*!< CRC (Bitfield-Mask: 0x01)                             */
#define RCC_DEEP_SLEEP_CR_DMA_Pos         (21UL)                    /*!< DMA (Bit 21)                                          */
#define RCC_DEEP_SLEEP_CR_DMA_Msk         (0x200000UL)              /*!< DMA (Bitfield-Mask: 0x01)                             */
#define RCC_DEEP_SLEEP_CR_TIM5_Pos        (20UL)                    /*!< TIM5 (Bit 20)                                         */
#define RCC_DEEP_SLEEP_CR_TIM5_Msk        (0x100000UL)              /*!< TIM5 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_TIM4_Pos        (19UL)                    /*!< TIM4 (Bit 19)                                         */
#define RCC_DEEP_SLEEP_CR_TIM4_Msk        (0x80000UL)               /*!< TIM4 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_ACMP_Pos        (18UL)                    /*!< ACMP (Bit 18)                                         */
#define RCC_DEEP_SLEEP_CR_ACMP_Msk        (0x40000UL)               /*!< ACMP (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_CAN_Pos         (17UL)                    /*!< CAN (Bit 17)                                          */
#define RCC_DEEP_SLEEP_CR_CAN_Msk         (0x20000UL)               /*!< CAN (Bitfield-Mask: 0x01)                             */
#define RCC_DEEP_SLEEP_CR_POSIF_Pos       (16UL)                    /*!< POSIF (Bit 16)                                        */
#define RCC_DEEP_SLEEP_CR_POSIF_Msk       (0x10000UL)               /*!< POSIF (Bitfield-Mask: 0x01)                           */
#define RCC_DEEP_SLEEP_CR_I2C_Pos         (15UL)                    /*!< I2C (Bit 15)                                          */
#define RCC_DEEP_SLEEP_CR_I2C_Msk         (0x8000UL)                /*!< I2C (Bitfield-Mask: 0x01)                             */
#define RCC_DEEP_SLEEP_CR_DAC_Pos         (14UL)                    /*!< DAC (Bit 14)                                          */
#define RCC_DEEP_SLEEP_CR_DAC_Msk         (0x4000UL)                /*!< DAC (Bitfield-Mask: 0x01)                             */
#define RCC_DEEP_SLEEP_CR_ADC_Pos         (13UL)                    /*!< ADC (Bit 13)                                          */
#define RCC_DEEP_SLEEP_CR_ADC_Msk         (0x2000UL)                /*!< ADC (Bitfield-Mask: 0x01)                             */
#define RCC_DEEP_SLEEP_CR_PVD_Pos         (12UL)                    /*!< PVD (Bit 12)                                          */
#define RCC_DEEP_SLEEP_CR_PVD_Msk         (0x1000UL)                /*!< PVD (Bitfield-Mask: 0x01)                             */
#define RCC_DEEP_SLEEP_CR_EPWM_Pos        (11UL)                    /*!< EPWM (Bit 11)                                         */
#define RCC_DEEP_SLEEP_CR_EPWM_Msk        (0x800UL)                 /*!< EPWM (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_CCT1_Pos        (10UL)                    /*!< CCT1 (Bit 10)                                         */
#define RCC_DEEP_SLEEP_CR_CCT1_Msk        (0x400UL)                 /*!< CCT1 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_CCT0_Pos        (9UL)                     /*!< CCT0 (Bit 9)                                          */
#define RCC_DEEP_SLEEP_CR_CCT0_Msk        (0x200UL)                 /*!< CCT0 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_TIM3_Pos        (8UL)                     /*!< TIM3 (Bit 8)                                          */
#define RCC_DEEP_SLEEP_CR_TIM3_Msk        (0x100UL)                 /*!< TIM3 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_TIM2_Pos        (7UL)                     /*!< TIM2 (Bit 7)                                          */
#define RCC_DEEP_SLEEP_CR_TIM2_Msk        (0x80UL)                  /*!< TIM2 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_TIM1_Pos        (6UL)                     /*!< TIM1 (Bit 6)                                          */
#define RCC_DEEP_SLEEP_CR_TIM1_Msk        (0x40UL)                  /*!< TIM1 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_TIM0_Pos        (5UL)                     /*!< TIM0 (Bit 5)                                          */
#define RCC_DEEP_SLEEP_CR_TIM0_Msk        (0x20UL)                  /*!< TIM0 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_SPI1_Pos        (4UL)                     /*!< SPI1 (Bit 4)                                          */
#define RCC_DEEP_SLEEP_CR_SPI1_Msk        (0x10UL)                  /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_SPI0_Pos        (3UL)                     /*!< SPI0 (Bit 3)                                          */
#define RCC_DEEP_SLEEP_CR_SPI0_Msk        (0x8UL)                   /*!< SPI0 (Bitfield-Mask: 0x01)                            */
#define RCC_DEEP_SLEEP_CR_UART2_Pos       (2UL)                     /*!< UART2 (Bit 2)                                         */
#define RCC_DEEP_SLEEP_CR_UART2_Msk       (0x4UL)                   /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define RCC_DEEP_SLEEP_CR_UART1_Pos       (1UL)                     /*!< UART1 (Bit 1)                                         */
#define RCC_DEEP_SLEEP_CR_UART1_Msk       (0x2UL)                   /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define RCC_DEEP_SLEEP_CR_UART0_Pos       (0UL)                     /*!< UART0 (Bit 0)                                         */
#define RCC_DEEP_SLEEP_CR_UART0_Msk       (0x1UL)                   /*!< UART0 (Bitfield-Mask: 0x01)                           */
/* ========================================================  STOP_CR  ======================================================== */
#define RCC_STOP_CR_FWKUP_EN_Pos          (2UL)                     /*!< FWKUP_EN (Bit 2)                                      */
#define RCC_STOP_CR_FWKUP_EN_Msk          (0x4UL)                   /*!< FWKUP_EN (Bitfield-Mask: 0x01)                        */
#define RCC_STOP_CR_LDO_EN_Pos            (1UL)                     /*!< LDO_EN (Bit 1)                                        */
#define RCC_STOP_CR_LDO_EN_Msk            (0x2UL)                   /*!< LDO_EN (Bitfield-Mask: 0x01)                          */
#define RCC_STOP_CR_LSCLK_EN_Pos          (0UL)                     /*!< LSCLK_EN (Bit 0)                                      */
#define RCC_STOP_CR_LSCLK_EN_Msk          (0x1UL)                   /*!< LSCLK_EN (Bitfield-Mask: 0x01)                        */
/* =======================================================  RESET_SR  ======================================================== */
#define RCC_RESET_SR_CLR_Pos              (16UL)                    /*!< CLR (Bit 16)                                          */
#define RCC_RESET_SR_CLR_Msk              (0x10000UL)               /*!< CLR (Bitfield-Mask: 0x01)                             */
#define RCC_RESET_SR_DSTB_DET_Pos         (7UL)                     /*!< DSTB_DET (Bit 7)                                      */
#define RCC_RESET_SR_DSTB_DET_Msk         (0x80UL)                  /*!< DSTB_DET (Bitfield-Mask: 0x01)                        */
#define RCC_RESET_SR_PVD_Pos              (6UL)                     /*!< PVD (Bit 6)                                           */
#define RCC_RESET_SR_PVD_Msk              (0x40UL)                  /*!< PVD (Bitfield-Mask: 0x01)                             */
#define RCC_RESET_SR_WDG_Pos              (5UL)                     /*!< WDG (Bit 5)                                           */
#define RCC_RESET_SR_WDG_Msk              (0x20UL)                  /*!< WDG (Bitfield-Mask: 0x01)                             */
#define RCC_RESET_SR_DSP_Pos              (4UL)                     /*!< DSP (Bit 4)                                           */
#define RCC_RESET_SR_DSP_Msk              (0x10UL)                  /*!< DSP (Bitfield-Mask: 0x01)                             */
#define RCC_RESET_SR_LOCKUP_Pos           (3UL)                     /*!< LOCKUP (Bit 3)                                        */
#define RCC_RESET_SR_LOCKUP_Msk           (0x8UL)                   /*!< LOCKUP (Bitfield-Mask: 0x01)                          */
#define RCC_RESET_SR_SW_Pos               (2UL)                     /*!< SW (Bit 2)                                            */
#define RCC_RESET_SR_SW_Msk               (0x4UL)                   /*!< SW (Bitfield-Mask: 0x01)                              */
#define RCC_RESET_SR_BUTTON_Pos           (1UL)                     /*!< BUTTON (Bit 1)                                        */
#define RCC_RESET_SR_BUTTON_Msk           (0x2UL)                   /*!< BUTTON (Bitfield-Mask: 0x01)                          */
#define RCC_RESET_SR_POR_Pos              (0UL)                     /*!< POR (Bit 0)                                           */
#define RCC_RESET_SR_POR_Msk              (0x1UL)                   /*!< POR (Bitfield-Mask: 0x01)                             */
/* =======================================================  SYSTEM_CR  ======================================================= */
#define RCC_SYSTEM_CR_LKUPRST_EN_Pos      (2UL)                     /*!< LKUPRST_EN (Bit 2)                                    */
#define RCC_SYSTEM_CR_LKUPRST_EN_Msk      (0x4UL)                   /*!< LKUPRST_EN (Bitfield-Mask: 0x01)                      */
#define RCC_SYSTEM_CR_REMAP_Pos           (0UL)                     /*!< REMAP (Bit 0)                                         */
#define RCC_SYSTEM_CR_REMAP_Msk           (0x3UL)                   /*!< REMAP (Bitfield-Mask: 0x03)                           */
/* ========================================================  LOCK_CR  ======================================================== */
#define RCC_LOCK_CR_KEY_Pos               (16UL)                    /*!< KEY (Bit 16)                                          */
#define RCC_LOCK_CR_KEY_Msk               (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define RCC_LOCK_CR_LOCK_EN_Pos           (0UL)                     /*!< LOCK_EN (Bit 0)                                       */
#define RCC_LOCK_CR_LOCK_EN_Msk           (0x1UL)                   /*!< LOCK_EN (Bitfield-Mask: 0x01)                         */
/* ========================================================  PLL_CR  ========================================================= */
#define RCC_PLL_CR_RDY_Pos                (9UL)                     /*!< RDY (Bit 9)                                           */
#define RCC_PLL_CR_RDY_Msk                (0x200UL)                 /*!< RDY (Bitfield-Mask: 0x01)                             */
#define RCC_PLL_CR_EN_Pos                 (8UL)                     /*!< EN (Bit 8)                                            */
#define RCC_PLL_CR_EN_Msk                 (0x100UL)                 /*!< EN (Bitfield-Mask: 0x01)                              */
#define RCC_PLL_CR_MULTPS_Pos             (4UL)                     /*!< MULTPS (Bit 4)                                        */
#define RCC_PLL_CR_MULTPS_Msk             (0xf0UL)                  /*!< MULTPS (Bitfield-Mask: 0x0f)                          */


/* =========================================================================================================================== */
/* ================                                            PGA                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define PGA_CR_PGA3_AMP_Pos               (28UL)                    /*!< PGA3_AMP (Bit 28)                                     */
#define PGA_CR_PGA3_AMP_Msk               (0x70000000UL)            /*!< PGA3_AMP (Bitfield-Mask: 0x07)                        */
#define PGA_CR_PGA2_AMP_Pos               (24UL)                    /*!< PGA2_AMP (Bit 24)                                     */
#define PGA_CR_PGA2_AMP_Msk               (0x7000000UL)             /*!< PGA2_AMP (Bitfield-Mask: 0x07)                        */
#define PGA_CR_PGA1_AMP_Pos               (20UL)                    /*!< PGA1_AMP (Bit 20)                                     */
#define PGA_CR_PGA1_AMP_Msk               (0x700000UL)              /*!< PGA1_AMP (Bitfield-Mask: 0x07)                        */
#define PGA_CR_PGA0_AMP_Pos               (16UL)                    /*!< PGA0_AMP (Bit 16)                                     */
#define PGA_CR_PGA0_AMP_Msk               (0x70000UL)               /*!< PGA0_AMP (Bitfield-Mask: 0x07)                        */
#define PGA_CR_PGA_SPEED_Pos              (13UL)                    /*!< PGA_SPEED (Bit 13)                                    */
#define PGA_CR_PGA_SPEED_Msk              (0x6000UL)                /*!< PGA_SPEED (Bitfield-Mask: 0x03)                       */
#define PGA_CR_OFFSET_SEL_Pos             (12UL)                    /*!< OFFSET_SEL (Bit 12)                                   */
#define PGA_CR_OFFSET_SEL_Msk             (0x1000UL)                /*!< OFFSET_SEL (Bitfield-Mask: 0x01)                      */
#define PGA_CR_PGA3_OFFSET_EN_Pos         (11UL)                    /*!< PGA3_OFFSET_EN (Bit 11)                               */
#define PGA_CR_PGA3_OFFSET_EN_Msk         (0x800UL)                 /*!< PGA3_OFFSET_EN (Bitfield-Mask: 0x01)                  */
#define PGA_CR_PGA2_OFFSET_EN_Pos         (10UL)                    /*!< PGA2_OFFSET_EN (Bit 10)                               */
#define PGA_CR_PGA2_OFFSET_EN_Msk         (0x400UL)                 /*!< PGA2_OFFSET_EN (Bitfield-Mask: 0x01)                  */
#define PGA_CR_PGA1_OFFSET_EN_Pos         (9UL)                     /*!< PGA1_OFFSET_EN (Bit 9)                                */
#define PGA_CR_PGA1_OFFSET_EN_Msk         (0x200UL)                 /*!< PGA1_OFFSET_EN (Bitfield-Mask: 0x01)                  */
#define PGA_CR_PGA0_OFFSET_EN_Pos         (8UL)                     /*!< PGA0_OFFSET_EN (Bit 8)                                */
#define PGA_CR_PGA0_OFFSET_EN_Msk         (0x100UL)                 /*!< PGA0_OFFSET_EN (Bitfield-Mask: 0x01)                  */
#define PGA_CR_PGA3_MODE_Pos              (7UL)                     /*!< PGA3_MODE (Bit 7)                                     */
#define PGA_CR_PGA3_MODE_Msk              (0x80UL)                  /*!< PGA3_MODE (Bitfield-Mask: 0x01)                       */
#define PGA_CR_PGA2_MODE_Pos              (6UL)                     /*!< PGA2_MODE (Bit 6)                                     */
#define PGA_CR_PGA2_MODE_Msk              (0x40UL)                  /*!< PGA2_MODE (Bitfield-Mask: 0x01)                       */
#define PGA_CR_PGA1_MODE_Pos              (5UL)                     /*!< PGA1_MODE (Bit 5)                                     */
#define PGA_CR_PGA1_MODE_Msk              (0x20UL)                  /*!< PGA1_MODE (Bitfield-Mask: 0x01)                       */
#define PGA_CR_PGA0_MODE_Pos              (4UL)                     /*!< PGA0_MODE (Bit 4)                                     */
#define PGA_CR_PGA0_MODE_Msk              (0x10UL)                  /*!< PGA0_MODE (Bitfield-Mask: 0x01)                       */
#define PGA_CR_PGA3_EN_Pos                (3UL)                     /*!< PGA3_EN (Bit 3)                                       */
#define PGA_CR_PGA3_EN_Msk                (0x8UL)                   /*!< PGA3_EN (Bitfield-Mask: 0x01)                         */
#define PGA_CR_PGA2_EN_Pos                (2UL)                     /*!< PGA2_EN (Bit 2)                                       */
#define PGA_CR_PGA2_EN_Msk                (0x4UL)                   /*!< PGA2_EN (Bitfield-Mask: 0x01)                         */
#define PGA_CR_PGA1_EN_Pos                (1UL)                     /*!< PGA1_EN (Bit 1)                                       */
#define PGA_CR_PGA1_EN_Msk                (0x2UL)                   /*!< PGA1_EN (Bitfield-Mask: 0x01)                         */
#define PGA_CR_PGA0_EN_Pos                (0UL)                     /*!< PGA0_EN (Bit 0)                                       */
#define PGA_CR_PGA0_EN_Msk                (0x1UL)                   /*!< PGA0_EN (Bitfield-Mask: 0x01)                         */


/* =========================================================================================================================== */
/* ================                                            DBG                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
#define DBG_CFG_EPWM_HALT_Pos             (10UL)                    /*!< EPWM_HALT (Bit 10)                                    */
#define DBG_CFG_EPWM_HALT_Msk             (0x400UL)                 /*!< EPWM_HALT (Bitfield-Mask: 0x01)                       */
#define DBG_CFG_LPTIM_HALT_Pos            (9UL)                     /*!< LPTIM_HALT (Bit 9)                                    */
#define DBG_CFG_LPTIM_HALT_Msk            (0x200UL)                 /*!< LPTIM_HALT (Bitfield-Mask: 0x01)                      */
#define DBG_CFG_CCT1_HALT_Pos             (8UL)                     /*!< CCT1_HALT (Bit 8)                                     */
#define DBG_CFG_CCT1_HALT_Msk             (0x100UL)                 /*!< CCT1_HALT (Bitfield-Mask: 0x01)                       */
#define DBG_CFG_CCT0_HALT_Pos             (7UL)                     /*!< CCT0_HALT (Bit 7)                                     */
#define DBG_CFG_CCT0_HALT_Msk             (0x80UL)                  /*!< CCT0_HALT (Bitfield-Mask: 0x01)                       */
#define DBG_CFG_TIM5_HALT_Pos             (6UL)                     /*!< TIM5_HALT (Bit 6)                                     */
#define DBG_CFG_TIM5_HALT_Msk             (0x40UL)                  /*!< TIM5_HALT (Bitfield-Mask: 0x01)                       */
#define DBG_CFG_TIM4_HALT_Pos             (5UL)                     /*!< TIM4_HALT (Bit 5)                                     */
#define DBG_CFG_TIM4_HALT_Msk             (0x20UL)                  /*!< TIM4_HALT (Bitfield-Mask: 0x01)                       */
#define DBG_CFG_TIM3_HALT_Pos             (4UL)                     /*!< TIM3_HALT (Bit 4)                                     */
#define DBG_CFG_TIM3_HALT_Msk             (0x10UL)                  /*!< TIM3_HALT (Bitfield-Mask: 0x01)                       */
#define DBG_CFG_TIM2_HALT_Pos             (3UL)                     /*!< TIM2_HALT (Bit 3)                                     */
#define DBG_CFG_TIM2_HALT_Msk             (0x8UL)                   /*!< TIM2_HALT (Bitfield-Mask: 0x01)                       */
#define DBG_CFG_TIM1_HALT_Pos             (2UL)                     /*!< TIM1_HALT (Bit 2)                                     */
#define DBG_CFG_TIM1_HALT_Msk             (0x4UL)                   /*!< TIM1_HALT (Bitfield-Mask: 0x01)                       */
#define DBG_CFG_TIM0_HALT_Pos             (1UL)                     /*!< TIM0_HALT (Bit 1)                                     */
#define DBG_CFG_TIM0_HALT_Msk             (0x2UL)                   /*!< TIM0_HALT (Bitfield-Mask: 0x01)                       */
#define DBG_CFG_WDG_HALT_Pos              (0UL)                     /*!< WDG_HALT (Bit 0)                                      */
#define DBG_CFG_WDG_HALT_Msk              (0x1UL)                   /*!< WDG_HALT (Bitfield-Mask: 0x01)                        */


/* =========================================================================================================================== */
/* ================                                            DES                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  UID_WORD0  ======================================================= */
#define DES_UID_WORD0_UID_Pos             (0UL)                     /*!< UID (Bit 0)                                           */
#define DES_UID_WORD0_UID_Msk             (0xffffffffUL)            /*!< UID (Bitfield-Mask: 0xffffffff)                       */
/* =======================================================  UID_WORD1  ======================================================= */
#define DES_UID_WORD1_UID_Pos             (0UL)                     /*!< UID (Bit 0)                                           */
#define DES_UID_WORD1_UID_Msk             (0xffffffffUL)            /*!< UID (Bitfield-Mask: 0xffffffff)                       */
/* =======================================================  UID_WORD2  ======================================================= */
#define DES_UID_WORD2_UID_Pos             (0UL)                     /*!< UID (Bit 0)                                           */
#define DES_UID_WORD2_UID_Msk             (0xffffffffUL)            /*!< UID (Bitfield-Mask: 0xffffffff)                       */
/* =======================================================  DEV_INFO0  ======================================================= */
#define DES_DEV_INFO0_PROD_TYPE_Pos       (28UL)                    /*!< PROD_TYPE (Bit 28)                                    */
#define DES_DEV_INFO0_PROD_TYPE_Msk       (0xf0000000UL)            /*!< PROD_TYPE (Bitfield-Mask: 0x0f)                       */
#define DES_DEV_INFO0_SUB_FAM_Pos         (12UL)                    /*!< SUB_FAM (Bit 12)                                      */
#define DES_DEV_INFO0_SUB_FAM_Msk         (0xffff000UL)             /*!< SUB_FAM (Bitfield-Mask: 0xffff)                       */
#define DES_DEV_INFO0_PIN_NUM_Pos         (8UL)                     /*!< PIN_NUM (Bit 8)                                       */
#define DES_DEV_INFO0_PIN_NUM_Msk         (0xf00UL)                 /*!< PIN_NUM (Bitfield-Mask: 0x0f)                         */
#define DES_DEV_INFO0_FLASH_SIZE_Pos      (4UL)                     /*!< FLASH_SIZE (Bit 4)                                    */
#define DES_DEV_INFO0_FLASH_SIZE_Msk      (0xf0UL)                  /*!< FLASH_SIZE (Bitfield-Mask: 0x0f)                      */
#define DES_DEV_INFO0_PKG_TYPE_Pos        (0UL)                     /*!< PKG_TYPE (Bit 0)                                      */
#define DES_DEV_INFO0_PKG_TYPE_Msk        (0xfUL)                   /*!< PKG_TYPE (Bitfield-Mask: 0x0f)                        */
/* =======================================================  DEV_INFO1  ======================================================= */
#define DES_DEV_INFO1_GATE_DRIVER_Pos     (28UL)                    /*!< GATE_DRIVER (Bit 28)                                  */
#define DES_DEV_INFO1_GATE_DRIVER_Msk     (0xf0000000UL)            /*!< GATE_DRIVER (Bitfield-Mask: 0x0f)                     */
#define DES_DEV_INFO1_INT_LDO_Pos         (24UL)                    /*!< INT_LDO (Bit 24)                                      */
#define DES_DEV_INFO1_INT_LDO_Msk         (0xf000000UL)             /*!< INT_LDO (Bitfield-Mask: 0x0f)                         */
#define DES_DEV_INFO1_INT_VERSION_Pos     (20UL)                    /*!< INT_VERSION (Bit 20)                                  */
#define DES_DEV_INFO1_INT_VERSION_Msk     (0xf00000UL)              /*!< INT_VERSION (Bitfield-Mask: 0x0f)                     */
#define DES_DEV_INFO1_TEMP_Pos            (16UL)                    /*!< TEMP (Bit 16)                                         */
#define DES_DEV_INFO1_TEMP_Msk            (0xf0000UL)               /*!< TEMP (Bitfield-Mask: 0x0f)                            */
#define DES_DEV_INFO1_PKG_VERSION_Pos     (12UL)                    /*!< PKG_VERSION (Bit 12)                                  */
#define DES_DEV_INFO1_PKG_VERSION_Msk     (0xf000UL)                /*!< PKG_VERSION (Bitfield-Mask: 0x0f)                     */
#define DES_DEV_INFO1_MCU_VERSION_Pos     (8UL)                     /*!< MCU_VERSION (Bit 8)                                   */
#define DES_DEV_INFO1_MCU_VERSION_Msk     (0xf00UL)                 /*!< MCU_VERSION (Bitfield-Mask: 0x0f)                     */
#define DES_DEV_INFO1_RAM_SIZE_Pos        (0UL)                     /*!< RAM_SIZE (Bit 0)                                      */
#define DES_DEV_INFO1_RAM_SIZE_Msk        (0xffUL)                  /*!< RAM_SIZE (Bitfield-Mask: 0xff)                        */


/* =========================================================================================================================== */
/* ================                                           TIM                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  CNT  ========================================================== */
#define TIM_CNT_CNT_Pos                   (0UL)                     /*!< CNT (Bit 0)                                           */
#define TIM_CNT_CNT_Msk                   (0xffffffffUL)            /*!< CNT (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  ARR  ========================================================== */
#define TIM_ARR_ARR_Pos                   (0UL)                     /*!< ARR (Bit 0)                                           */
#define TIM_ARR_ARR_Msk                   (0xffffffffUL)            /*!< ARR (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  CR  =========================================================== */
#define TIM_CR_DE_Pos                     (3UL)                     /*!< DE (Bit 3)                                            */
#define TIM_CR_DE_Msk                     (0x8UL)                   /*!< DE (Bitfield-Mask: 0x01)                              */
#define TIM_CR_IE_Pos                     (2UL)                     /*!< IE (Bit 2)                                            */
#define TIM_CR_IE_Msk                     (0x4UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
#define TIM_CR_SINGLE_Pos                 (1UL)                     /*!< SINGLE (Bit 1)                                        */
#define TIM_CR_SINGLE_Msk                 (0x2UL)                   /*!< SINGLE (Bitfield-Mask: 0x01)                          */
#define TIM_CR_EN_Pos                     (0UL)                     /*!< EN (Bit 0)                                            */
#define TIM_CR_EN_Msk                     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  SR  =========================================================== */
#define TIM_SR_IF_Pos                     (0UL)                     /*!< IF (Bit 0)                                            */
#define TIM_SR_IF_Msk                     (0x1UL)                   /*!< IF (Bitfield-Mask: 0x01)                              */


/* =========================================================================================================================== */
/* ================                                           CCT                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  CNT  ========================================================== */
#define CCT_CNT_CNT_Pos                   (0UL)                     /*!< CNT (Bit 0)                                           */
#define CCT_CNT_CNT_Msk                   (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  ARR  ========================================================== */
#define CCT_ARR_ARR_Pos                   (0UL)                     /*!< ARR (Bit 0)                                           */
#define CCT_ARR_ARR_Msk                   (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CR  =========================================================== */
#define CCT_CR_IN1_ACMP_SEL_Pos           (28UL)                    /*!< IN1_ACMP_SEL (Bit 28)                                 */
#define CCT_CR_IN1_ACMP_SEL_Msk           (0x30000000UL)            /*!< IN1_ACMP_SEL (Bitfield-Mask: 0x03)                    */
#define CCT_CR_IN1_SEL_Pos                (27UL)                    /*!< IN1_SEL (Bit 27)                                      */
#define CCT_CR_IN1_SEL_Msk                (0x8000000UL)             /*!< IN1_SEL (Bitfield-Mask: 0x01)                         */
#define CCT_CR_IN0_ACMP_SEL_Pos           (25UL)                    /*!< IN0_ACMP_SEL (Bit 25)                                 */
#define CCT_CR_IN0_ACMP_SEL_Msk           (0x6000000UL)             /*!< IN0_ACMP_SEL (Bitfield-Mask: 0x03)                    */
#define CCT_CR_IN0_SEL_Pos                (24UL)                    /*!< IN0_SEL (Bit 24)                                      */
#define CCT_CR_IN0_SEL_Msk                (0x1000000UL)             /*!< IN0_SEL (Bitfield-Mask: 0x01)                         */
#define CCT_CR_DMA_SRC_SEL_Pos            (16UL)                    /*!< DMA_SRC_SEL (Bit 16)                                  */
#define CCT_CR_DMA_SRC_SEL_Msk            (0x70000UL)               /*!< DMA_SRC_SEL (Bitfield-Mask: 0x07)                     */
#define CCT_CR_CH1_CMP_IE_Pos             (15UL)                    /*!< CH1_CMP_IE (Bit 15)                                   */
#define CCT_CR_CH1_CMP_IE_Msk             (0x8000UL)                /*!< CH1_CMP_IE (Bitfield-Mask: 0x01)                      */
#define CCT_CR_CH0_CMP_IE_Pos             (14UL)                    /*!< CH0_CMP_IE (Bit 14)                                   */
#define CCT_CR_CH0_CMP_IE_Msk             (0x4000UL)                /*!< CH0_CMP_IE (Bitfield-Mask: 0x01)                      */
#define CCT_CR_CH1_CAP_IE_Pos             (13UL)                    /*!< CH1_CAP_IE (Bit 13)                                   */
#define CCT_CR_CH1_CAP_IE_Msk             (0x2000UL)                /*!< CH1_CAP_IE (Bitfield-Mask: 0x01)                      */
#define CCT_CR_CH0_CAP_IE_Pos             (12UL)                    /*!< CH0_CAP_IE (Bit 12)                                   */
#define CCT_CR_CH0_CAP_IE_Msk             (0x1000UL)                /*!< CH0_CAP_IE (Bitfield-Mask: 0x01)                      */
#define CCT_CR_LVAL_IE_Pos                (11UL)                    /*!< LVAL_IE (Bit 11)                                      */
#define CCT_CR_LVAL_IE_Msk                (0x800UL)                 /*!< LVAL_IE (Bitfield-Mask: 0x01)                         */
#define CCT_CR_CLK_DIV_Pos                (8UL)                     /*!< CLK_DIV (Bit 8)                                       */
#define CCT_CR_CLK_DIV_Msk                (0x700UL)                 /*!< CLK_DIV (Bitfield-Mask: 0x07)                         */
#define CCT_CR_CH1_MODE_Pos               (5UL)                     /*!< CH1_MODE (Bit 5)                                      */
#define CCT_CR_CH1_MODE_Msk               (0x20UL)                  /*!< CH1_MODE (Bitfield-Mask: 0x01)                        */
#define CCT_CR_CH0_MODE_Pos               (4UL)                     /*!< CH0_MODE (Bit 4)                                      */
#define CCT_CR_CH0_MODE_Msk               (0x10UL)                  /*!< CH0_MODE (Bitfield-Mask: 0x01)                        */
#define CCT_CR_CH1_EN_Pos                 (3UL)                     /*!< CH1_EN (Bit 3)                                        */
#define CCT_CR_CH1_EN_Msk                 (0x8UL)                   /*!< CH1_EN (Bitfield-Mask: 0x01)                          */
#define CCT_CR_CH0_EN_Pos                 (2UL)                     /*!< CH0_EN (Bit 2)                                        */
#define CCT_CR_CH0_EN_Msk                 (0x4UL)                   /*!< CH0_EN (Bitfield-Mask: 0x01)                          */
#define CCT_CR_SINGLE_Pos                 (1UL)                     /*!< SINGLE (Bit 1)                                        */
#define CCT_CR_SINGLE_Msk                 (0x2UL)                   /*!< SINGLE (Bitfield-Mask: 0x01)                          */
#define CCT_CR_EN_Pos                     (0UL)                     /*!< EN (Bit 0)                                            */
#define CCT_CR_EN_Msk                     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  SR  =========================================================== */
#define CCT_SR_CH1_CMP_IF_Pos             (9UL)                     /*!< CH1_CMP_IF (Bit 9)                                    */
#define CCT_SR_CH1_CMP_IF_Msk             (0x200UL)                 /*!< CH1_CMP_IF (Bitfield-Mask: 0x01)                      */
#define CCT_SR_CH0_CMP_IF_Pos             (8UL)                     /*!< CH0_CMP_IF (Bit 8)                                    */
#define CCT_SR_CH0_CMP_IF_Msk             (0x100UL)                 /*!< CH0_CMP_IF (Bitfield-Mask: 0x01)                      */
#define CCT_SR_CH1_CAP_FE_Pos             (6UL)                     /*!< CH1_CAP_FE (Bit 6)                                    */
#define CCT_SR_CH1_CAP_FE_Msk             (0x40UL)                  /*!< CH1_CAP_FE (Bitfield-Mask: 0x01)                      */
#define CCT_SR_CH1_CAP_RE_Pos             (5UL)                     /*!< CH1_CAP_RE (Bit 5)                                    */
#define CCT_SR_CH1_CAP_RE_Msk             (0x20UL)                  /*!< CH1_CAP_RE (Bitfield-Mask: 0x01)                      */
#define CCT_SR_CH0_CAP_FE_Pos             (4UL)                     /*!< CH0_CAP_FE (Bit 4)                                    */
#define CCT_SR_CH0_CAP_FE_Msk             (0x10UL)                  /*!< CH0_CAP_FE (Bitfield-Mask: 0x01)                      */
#define CCT_SR_CH0_CAP_RE_Pos             (3UL)                     /*!< CH0_CAP_RE (Bit 3)                                    */
#define CCT_SR_CH0_CAP_RE_Msk             (0x8UL)                   /*!< CH0_CAP_RE (Bitfield-Mask: 0x01)                      */
#define CCT_SR_CH1_CAP_IF_Pos             (2UL)                     /*!< CH1_CAP_IF (Bit 2)                                    */
#define CCT_SR_CH1_CAP_IF_Msk             (0x4UL)                   /*!< CH1_CAP_IF (Bitfield-Mask: 0x01)                      */
#define CCT_SR_CH0_CAP_IF_Pos             (1UL)                     /*!< CH0_CAP_IF (Bit 1)                                    */
#define CCT_SR_CH0_CAP_IF_Msk             (0x2UL)                   /*!< CH0_CAP_IF (Bitfield-Mask: 0x01)                      */
#define CCT_SR_LVAL_IF_Pos                (0UL)                     /*!< LVAL_IF (Bit 0)                                       */
#define CCT_SR_LVAL_IF_Msk                (0x1UL)                   /*!< LVAL_IF (Bitfield-Mask: 0x01)                         */
/* ========================================================  CAP_CFG  ======================================================== */
#define CCT_CAP_CFG_CH1_EDGE_Pos          (13UL)                    /*!< CH1_EDGE (Bit 13)                                     */
#define CCT_CAP_CFG_CH1_EDGE_Msk          (0x6000UL)                /*!< CH1_EDGE (Bitfield-Mask: 0x03)                        */
#define CCT_CAP_CFG_CH1_CNT_CLR_Pos       (12UL)                    /*!< CH1_CNT_CLR (Bit 12)                                  */
#define CCT_CAP_CFG_CH1_CNT_CLR_Msk       (0x1000UL)                /*!< CH1_CNT_CLR (Bitfield-Mask: 0x01)                     */
#define CCT_CAP_CFG_CH1_FLT_LEN_Pos       (10UL)                    /*!< CH1_FLT_LEN (Bit 10)                                  */
#define CCT_CAP_CFG_CH1_FLT_LEN_Msk       (0xc00UL)                 /*!< CH1_FLT_LEN (Bitfield-Mask: 0x03)                     */
#define CCT_CAP_CFG_CH1_FLT_SAMPLE_Pos    (8UL)                     /*!< CH1_FLT_SAMPLE (Bit 8)                                */
#define CCT_CAP_CFG_CH1_FLT_SAMPLE_Msk    (0x300UL)                 /*!< CH1_FLT_SAMPLE (Bitfield-Mask: 0x03)                  */
#define CCT_CAP_CFG_CH0_EDGE_Pos          (5UL)                     /*!< CH0_EDGE (Bit 5)                                      */
#define CCT_CAP_CFG_CH0_EDGE_Msk          (0x60UL)                  /*!< CH0_EDGE (Bitfield-Mask: 0x03)                        */
#define CCT_CAP_CFG_CH0_CNT_CLR_Pos       (4UL)                     /*!< CH0_CNT_CLR (Bit 4)                                   */
#define CCT_CAP_CFG_CH0_CNT_CLR_Msk       (0x10UL)                  /*!< CH0_CNT_CLR (Bitfield-Mask: 0x01)                     */
#define CCT_CAP_CFG_CH0_FLT_LEN_Pos       (2UL)                     /*!< CH0_FLT_LEN (Bit 2)                                   */
#define CCT_CAP_CFG_CH0_FLT_LEN_Msk       (0xcUL)                   /*!< CH0_FLT_LEN (Bitfield-Mask: 0x03)                     */
#define CCT_CAP_CFG_CH0_FLT_SAMPLE_Pos    (0UL)                     /*!< CH0_FLT_SAMPLE (Bit 0)                                */
#define CCT_CAP_CFG_CH0_FLT_SAMPLE_Msk    (0x3UL)                   /*!< CH0_FLT_SAMPLE (Bitfield-Mask: 0x03)                  */
/* ========================================================  CMP_CFG  ======================================================== */
#define CCT_CMP_CFG_CH1_INIT_O_Pos        (1UL)                     /*!< CH1_INIT_O (Bit 1)                                    */
#define CCT_CMP_CFG_CH1_INIT_O_Msk        (0x2UL)                   /*!< CH1_INIT_O (Bitfield-Mask: 0x01)                      */
#define CCT_CMP_CFG_CH0_INIT_O_Pos        (0UL)                     /*!< CH0_INIT_O (Bit 0)                                    */
#define CCT_CMP_CFG_CH0_INIT_O_Msk        (0x1UL)                   /*!< CH0_INIT_O (Bitfield-Mask: 0x01)                      */
/* =======================================================  CH0_VALUE  ======================================================= */
#define CCT_CH0_VALUE_VAL_Pos             (0UL)                     /*!< VAL (Bit 0)                                           */
#define CCT_CH0_VALUE_VAL_Msk             (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH1_VALUE  ======================================================= */
#define CCT_CH1_VALUE_VAL_Pos             (0UL)                     /*!< VAL (Bit 0)                                           */
#define CCT_CH1_VALUE_VAL_Msk             (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */


/* =========================================================================================================================== */
/* ================                                           EPWM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CNT  ========================================================== */
#define EPWM_CNT_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define EPWM_CNT_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  ARR  ========================================================== */
#define EPWM_ARR_ARR_Pos                  (0UL)                     /*!< ARR (Bit 0)                                           */
#define EPWM_ARR_ARR_Msk                  (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CR  =========================================================== */
#define EPWM_CR_PERIOD_DE_Pos             (16UL)                    /*!< PERIOD_DE (Bit 16)                                    */
#define EPWM_CR_PERIOD_DE_Msk             (0x10000UL)               /*!< PERIOD_DE (Bitfield-Mask: 0x01)                       */
#define EPWM_CR_STOP_IE_Pos               (15UL)                    /*!< STOP_IE (Bit 15)                                      */
#define EPWM_CR_STOP_IE_Msk               (0x8000UL)                /*!< STOP_IE (Bitfield-Mask: 0x01)                         */
#define EPWM_CR_ADC_CMP2_IE_Pos           (14UL)                    /*!< ADC_CMP2_IE (Bit 14)                                  */
#define EPWM_CR_ADC_CMP2_IE_Msk           (0x4000UL)                /*!< ADC_CMP2_IE (Bitfield-Mask: 0x01)                     */
#define EPWM_CR_ADC_CMP1_IE_Pos           (13UL)                    /*!< ADC_CMP1_IE (Bit 13)                                  */
#define EPWM_CR_ADC_CMP1_IE_Msk           (0x2000UL)                /*!< ADC_CMP1_IE (Bitfield-Mask: 0x01)                     */
#define EPWM_CR_PERIOD_IE_Pos             (12UL)                    /*!< PERIOD_IE (Bit 12)                                    */
#define EPWM_CR_PERIOD_IE_Msk             (0x1000UL)                /*!< PERIOD_IE (Bitfield-Mask: 0x01)                       */
#define EPWM_CR_LOAD_VAL_IE_Pos           (11UL)                    /*!< LOAD_VAL_IE (Bit 11)                                  */
#define EPWM_CR_LOAD_VAL_IE_Msk           (0x800UL)                 /*!< LOAD_VAL_IE (Bitfield-Mask: 0x01)                     */
#define EPWM_CR_CLK_DIV_Pos               (8UL)                     /*!< CLK_DIV (Bit 8)                                       */
#define EPWM_CR_CLK_DIV_Msk               (0x700UL)                 /*!< CLK_DIV (Bitfield-Mask: 0x07)                         */
#define EPWM_CR_CH3_EN_Pos                (7UL)                     /*!< CH3_EN (Bit 7)                                        */
#define EPWM_CR_CH3_EN_Msk                (0x80UL)                  /*!< CH3_EN (Bitfield-Mask: 0x01)                          */
#define EPWM_CR_CH2_EN_Pos                (6UL)                     /*!< CH2_EN (Bit 6)                                        */
#define EPWM_CR_CH2_EN_Msk                (0x40UL)                  /*!< CH2_EN (Bitfield-Mask: 0x01)                          */
#define EPWM_CR_CH1_EN_Pos                (5UL)                     /*!< CH1_EN (Bit 5)                                        */
#define EPWM_CR_CH1_EN_Msk                (0x20UL)                  /*!< CH1_EN (Bitfield-Mask: 0x01)                          */
#define EPWM_CR_CH0_EN_Pos                (4UL)                     /*!< CH0_EN (Bit 4)                                        */
#define EPWM_CR_CH0_EN_Msk                (0x10UL)                  /*!< CH0_EN (Bitfield-Mask: 0x01)                          */
#define EPWM_CR_MODE_Pos                  (2UL)                     /*!< MODE (Bit 2)                                          */
#define EPWM_CR_MODE_Msk                  (0x4UL)                   /*!< MODE (Bitfield-Mask: 0x01)                            */
#define EPWM_CR_SINGLE_Pos                (1UL)                     /*!< SINGLE (Bit 1)                                        */
#define EPWM_CR_SINGLE_Msk                (0x2UL)                   /*!< SINGLE (Bitfield-Mask: 0x01)                          */
#define EPWM_CR_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define EPWM_CR_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  SR  =========================================================== */
#define EPWM_SR_STOP_IF_Pos               (4UL)                     /*!< STOP_IF (Bit 4)                                       */
#define EPWM_SR_STOP_IF_Msk               (0x10UL)                  /*!< STOP_IF (Bitfield-Mask: 0x01)                         */
#define EPWM_SR_ADC_CMP2_IF_Pos           (3UL)                     /*!< ADC_CMP2_IF (Bit 3)                                   */
#define EPWM_SR_ADC_CMP2_IF_Msk           (0x8UL)                   /*!< ADC_CMP2_IF (Bitfield-Mask: 0x01)                     */
#define EPWM_SR_ADC_CMP1_IF_Pos           (2UL)                     /*!< ADC_CMP1_IF (Bit 2)                                   */
#define EPWM_SR_ADC_CMP1_IF_Msk           (0x4UL)                   /*!< ADC_CMP1_IF (Bitfield-Mask: 0x01)                     */
#define EPWM_SR_PERIOD_IF_Pos             (1UL)                     /*!< PERIOD_IF (Bit 1)                                     */
#define EPWM_SR_PERIOD_IF_Msk             (0x2UL)                   /*!< PERIOD_IF (Bitfield-Mask: 0x01)                       */
#define EPWM_SR_LOAD_VAL_IF_Pos           (0UL)                     /*!< LOAD_VAL_IF (Bit 0)                                   */
#define EPWM_SR_LOAD_VAL_IF_Msk           (0x1UL)                   /*!< LOAD_VAL_IF (Bitfield-Mask: 0x01)                     */
/* ========================================================  CMP_CFG  ======================================================== */
#define EPWM_CMP_CFG_ADC_CMP2_DIR_Pos     (19UL)                    /*!< ADC_CMP2_DIR (Bit 19)                                 */
#define EPWM_CMP_CFG_ADC_CMP2_DIR_Msk     (0x80000UL)               /*!< ADC_CMP2_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_ADC_CMP2_EN_Pos      (18UL)                    /*!< ADC_CMP2_EN (Bit 18)                                  */
#define EPWM_CMP_CFG_ADC_CMP2_EN_Msk      (0x40000UL)               /*!< ADC_CMP2_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_CMP_CFG_ADC_CMP1_DIR_Pos     (17UL)                    /*!< ADC_CMP1_DIR (Bit 17)                                 */
#define EPWM_CMP_CFG_ADC_CMP1_DIR_Msk     (0x20000UL)               /*!< ADC_CMP1_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_ADC_CMP1_EN_Pos      (16UL)                    /*!< ADC_CMP1_EN (Bit 16)                                  */
#define EPWM_CMP_CFG_ADC_CMP1_EN_Msk      (0x10000UL)               /*!< ADC_CMP1_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_CMP_CFG_CH3_CMP2_DIR_Pos     (15UL)                    /*!< CH3_CMP2_DIR (Bit 15)                                 */
#define EPWM_CMP_CFG_CH3_CMP2_DIR_Msk     (0x8000UL)                /*!< CH3_CMP2_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_CH3_CMP2_EN_Pos      (14UL)                    /*!< CH3_CMP2_EN (Bit 14)                                  */
#define EPWM_CMP_CFG_CH3_CMP2_EN_Msk      (0x4000UL)                /*!< CH3_CMP2_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_CMP_CFG_CH3_CMP1_DIR_Pos     (13UL)                    /*!< CH3_CMP1_DIR (Bit 13)                                 */
#define EPWM_CMP_CFG_CH3_CMP1_DIR_Msk     (0x2000UL)                /*!< CH3_CMP1_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_CH3_CMP1_EN_Pos      (12UL)                    /*!< CH3_CMP1_EN (Bit 12)                                  */
#define EPWM_CMP_CFG_CH3_CMP1_EN_Msk      (0x1000UL)                /*!< CH3_CMP1_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_CMP_CFG_CH2_CMP2_DIR_Pos     (11UL)                    /*!< CH2_CMP2_DIR (Bit 11)                                 */
#define EPWM_CMP_CFG_CH2_CMP2_DIR_Msk     (0x800UL)                 /*!< CH2_CMP2_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_CH2_CMP2_EN_Pos      (10UL)                    /*!< CH2_CMP2_EN (Bit 10)                                  */
#define EPWM_CMP_CFG_CH2_CMP2_EN_Msk      (0x400UL)                 /*!< CH2_CMP2_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_CMP_CFG_CH2_CMP1_DIR_Pos     (9UL)                     /*!< CH2_CMP1_DIR (Bit 9)                                  */
#define EPWM_CMP_CFG_CH2_CMP1_DIR_Msk     (0x200UL)                 /*!< CH2_CMP1_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_CH2_CMP1_EN_Pos      (8UL)                     /*!< CH2_CMP1_EN (Bit 8)                                   */
#define EPWM_CMP_CFG_CH2_CMP1_EN_Msk      (0x100UL)                 /*!< CH2_CMP1_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_CMP_CFG_CH1_CMP2_DIR_Pos     (7UL)                     /*!< CH1_CMP2_DIR (Bit 7)                                  */
#define EPWM_CMP_CFG_CH1_CMP2_DIR_Msk     (0x80UL)                  /*!< CH1_CMP2_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_CH1_CMP2_EN_Pos      (6UL)                     /*!< CH1_CMP2_EN (Bit 6)                                   */
#define EPWM_CMP_CFG_CH1_CMP2_EN_Msk      (0x40UL)                  /*!< CH1_CMP2_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_CMP_CFG_CH1_CMP1_DIR_Pos     (5UL)                     /*!< CH1_CMP1_DIR (Bit 5)                                  */
#define EPWM_CMP_CFG_CH1_CMP1_DIR_Msk     (0x20UL)                  /*!< CH1_CMP1_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_CH1_CMP1_EN_Pos      (4UL)                     /*!< CH1_CMP1_EN (Bit 4)                                   */
#define EPWM_CMP_CFG_CH1_CMP1_EN_Msk      (0x10UL)                  /*!< CH1_CMP1_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_CMP_CFG_CH0_CMP2_DIR_Pos     (3UL)                     /*!< CH0_CMP2_DIR (Bit 3)                                  */
#define EPWM_CMP_CFG_CH0_CMP2_DIR_Msk     (0x8UL)                   /*!< CH0_CMP2_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_CH0_CMP2_EN_Pos      (2UL)                     /*!< CH0_CMP2_EN (Bit 2)                                   */
#define EPWM_CMP_CFG_CH0_CMP2_EN_Msk      (0x4UL)                   /*!< CH0_CMP2_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_CMP_CFG_CH0_CMP1_DIR_Pos     (1UL)                     /*!< CH0_CMP1_DIR (Bit 1)                                  */
#define EPWM_CMP_CFG_CH0_CMP1_DIR_Msk     (0x2UL)                   /*!< CH0_CMP1_DIR (Bitfield-Mask: 0x01)                    */
#define EPWM_CMP_CFG_CH0_CMP1_EN_Pos      (0UL)                     /*!< CH0_CMP1_EN (Bit 0)                                   */
#define EPWM_CMP_CFG_CH0_CMP1_EN_Msk      (0x1UL)                   /*!< CH0_CMP1_EN (Bitfield-Mask: 0x01)                     */
/* =======================================================  ADC_CMP1  ======================================================== */
#define EPWM_ADC_CMP1_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_ADC_CMP1_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* =======================================================  ADC_CMP2  ======================================================== */
#define EPWM_ADC_CMP2_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_ADC_CMP2_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* =======================================================  CH0_CMP1  ======================================================== */
#define EPWM_CH0_CMP1_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_CH0_CMP1_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* =======================================================  CH0_CMP2  ======================================================== */
#define EPWM_CH0_CMP2_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_CH0_CMP2_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* =======================================================  CH1_CMP1  ======================================================== */
#define EPWM_CH1_CMP1_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_CH1_CMP1_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* =======================================================  CH1_CMP2  ======================================================== */
#define EPWM_CH1_CMP2_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_CH1_CMP2_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* =======================================================  CH2_CMP1  ======================================================== */
#define EPWM_CH2_CMP1_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_CH2_CMP1_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* =======================================================  CH2_CMP2  ======================================================== */
#define EPWM_CH2_CMP2_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_CH2_CMP2_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* =======================================================  CH3_CMP1  ======================================================== */
#define EPWM_CH3_CMP1_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_CH3_CMP1_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* =======================================================  CH3_CMP2  ======================================================== */
#define EPWM_CH3_CMP2_CMP_VAL_Pos         (0UL)                     /*!< CMP_VAL (Bit 0)                                       */
#define EPWM_CH3_CMP2_CMP_VAL_Msk         (0xffffUL)                /*!< CMP_VAL (Bitfield-Mask: 0xffff)                       */
/* ========================================================  UPDATE  ========================================================= */
#define EPWM_UPDATE_UPDATE_Pos            (0UL)                     /*!< UPDATE (Bit 0)                                        */
#define EPWM_UPDATE_UPDATE_Msk            (0x1UL)                   /*!< UPDATE (Bitfield-Mask: 0x01)                          */
/* =========================================================  CH_CR  ========================================================= */
#define EPWM_CH_CR_CH3_PP_Pos             (31UL)                    /*!< CH3_PP (Bit 31)                                       */
#define EPWM_CH_CR_CH3_PP_Msk             (0x80000000UL)            /*!< CH3_PP (Bitfield-Mask: 0x01)                          */
#define EPWM_CH_CR_CH3_NP_Pos             (30UL)                    /*!< CH3_NP (Bit 30)                                       */
#define EPWM_CH_CR_CH3_NP_Msk             (0x40000000UL)            /*!< CH3_NP (Bitfield-Mask: 0x01)                          */
#define EPWM_CH_CR_CH2_PP_Pos             (29UL)                    /*!< CH2_PP (Bit 29)                                       */
#define EPWM_CH_CR_CH2_PP_Msk             (0x20000000UL)            /*!< CH2_PP (Bitfield-Mask: 0x01)                          */
#define EPWM_CH_CR_CH2_NP_Pos             (28UL)                    /*!< CH2_NP (Bit 28)                                       */
#define EPWM_CH_CR_CH2_NP_Msk             (0x10000000UL)            /*!< CH2_NP (Bitfield-Mask: 0x01)                          */
#define EPWM_CH_CR_CH1_PP_Pos             (27UL)                    /*!< CH1_PP (Bit 27)                                       */
#define EPWM_CH_CR_CH1_PP_Msk             (0x8000000UL)             /*!< CH1_PP (Bitfield-Mask: 0x01)                          */
#define EPWM_CH_CR_CH1_NP_Pos             (26UL)                    /*!< CH1_NP (Bit 26)                                       */
#define EPWM_CH_CR_CH1_NP_Msk             (0x4000000UL)             /*!< CH1_NP (Bitfield-Mask: 0x01)                          */
#define EPWM_CH_CR_CH0_PP_Pos             (25UL)                    /*!< CH0_PP (Bit 25)                                       */
#define EPWM_CH_CR_CH0_PP_Msk             (0x2000000UL)             /*!< CH0_PP (Bitfield-Mask: 0x01)                          */
#define EPWM_CH_CR_CH0_NP_Pos             (24UL)                    /*!< CH0_NP (Bit 24)                                       */
#define EPWM_CH_CR_CH0_NP_Msk             (0x1000000UL)             /*!< CH0_NP (Bitfield-Mask: 0x01)                          */
#define EPWM_CH_CR_CH3_INIT_O_Pos         (19UL)                    /*!< CH3_INIT_O (Bit 19)                                   */
#define EPWM_CH_CR_CH3_INIT_O_Msk         (0x80000UL)               /*!< CH3_INIT_O (Bitfield-Mask: 0x01)                      */
#define EPWM_CH_CR_CH2_INIT_O_Pos         (18UL)                    /*!< CH2_INIT_O (Bit 18)                                   */
#define EPWM_CH_CR_CH2_INIT_O_Msk         (0x40000UL)               /*!< CH2_INIT_O (Bitfield-Mask: 0x01)                      */
#define EPWM_CH_CR_CH1_INIT_O_Pos         (17UL)                    /*!< CH1_INIT_O (Bit 17)                                   */
#define EPWM_CH_CR_CH1_INIT_O_Msk         (0x20000UL)               /*!< CH1_INIT_O (Bitfield-Mask: 0x01)                      */
#define EPWM_CH_CR_CH0_INIT_O_Pos         (16UL)                    /*!< CH0_INIT_O (Bit 16)                                   */
#define EPWM_CH_CR_CH0_INIT_O_Msk         (0x10000UL)               /*!< CH0_INIT_O (Bitfield-Mask: 0x01)                      */
#define EPWM_CH_CR_CH3_CMP2_ACT_Pos       (14UL)                    /*!< CH3_CMP2_ACT (Bit 14)                                 */
#define EPWM_CH_CR_CH3_CMP2_ACT_Msk       (0xc000UL)                /*!< CH3_CMP2_ACT (Bitfield-Mask: 0x03)                    */
#define EPWM_CH_CR_CH3_CMP1_ACT_Pos       (12UL)                    /*!< CH3_CMP1_ACT (Bit 12)                                 */
#define EPWM_CH_CR_CH3_CMP1_ACT_Msk       (0x3000UL)                /*!< CH3_CMP1_ACT (Bitfield-Mask: 0x03)                    */
#define EPWM_CH_CR_CH2_CMP2_ACT_Pos       (10UL)                    /*!< CH2_CMP2_ACT (Bit 10)                                 */
#define EPWM_CH_CR_CH2_CMP2_ACT_Msk       (0xc00UL)                 /*!< CH2_CMP2_ACT (Bitfield-Mask: 0x03)                    */
#define EPWM_CH_CR_CH2_CMP1_ACT_Pos       (8UL)                     /*!< CH2_CMP1_ACT (Bit 8)                                  */
#define EPWM_CH_CR_CH2_CMP1_ACT_Msk       (0x300UL)                 /*!< CH2_CMP1_ACT (Bitfield-Mask: 0x03)                    */
#define EPWM_CH_CR_CH1_CMP2_ACT_Pos       (6UL)                     /*!< CH1_CMP2_ACT (Bit 6)                                  */
#define EPWM_CH_CR_CH1_CMP2_ACT_Msk       (0xc0UL)                  /*!< CH1_CMP2_ACT (Bitfield-Mask: 0x03)                    */
#define EPWM_CH_CR_CH1_CMP1_ACT_Pos       (4UL)                     /*!< CH1_CMP1_ACT (Bit 4)                                  */
#define EPWM_CH_CR_CH1_CMP1_ACT_Msk       (0x30UL)                  /*!< CH1_CMP1_ACT (Bitfield-Mask: 0x03)                    */
#define EPWM_CH_CR_CH0_CMP2_ACT_Pos       (2UL)                     /*!< CH0_CMP2_ACT (Bit 2)                                  */
#define EPWM_CH_CR_CH0_CMP2_ACT_Msk       (0xcUL)                   /*!< CH0_CMP2_ACT (Bitfield-Mask: 0x03)                    */
#define EPWM_CH_CR_CH0_CMP1_ACT_Pos       (0UL)                     /*!< CH0_CMP1_ACT (Bit 0)                                  */
#define EPWM_CH_CR_CH0_CMP1_ACT_Msk       (0x3UL)                   /*!< CH0_CMP1_ACT (Bitfield-Mask: 0x03)                    */
/* ========================================================  OUT_CR  ========================================================= */
#define EPWM_OUT_CR_CH3_P_FORCE_O_Pos     (15UL)                    /*!< CH3_P_FORCE_O (Bit 15)                                */
#define EPWM_OUT_CR_CH3_P_FORCE_O_Msk     (0x8000UL)                /*!< CH3_P_FORCE_O (Bitfield-Mask: 0x01)                   */
#define EPWM_OUT_CR_CH3_N_FORCE_O_Pos     (14UL)                    /*!< CH3_N_FORCE_O (Bit 14)                                */
#define EPWM_OUT_CR_CH3_N_FORCE_O_Msk     (0x4000UL)                /*!< CH3_N_FORCE_O (Bitfield-Mask: 0x01)                   */
#define EPWM_OUT_CR_CH3_P_FORCE_EN_Pos    (13UL)                    /*!< CH3_P_FORCE_EN (Bit 13)                               */
#define EPWM_OUT_CR_CH3_P_FORCE_EN_Msk    (0x2000UL)                /*!< CH3_P_FORCE_EN (Bitfield-Mask: 0x01)                  */
#define EPWM_OUT_CR_CH3_N_FORCE_EN_Pos    (12UL)                    /*!< CH3_N_FORCE_EN (Bit 12)                               */
#define EPWM_OUT_CR_CH3_N_FORCE_EN_Msk    (0x1000UL)                /*!< CH3_N_FORCE_EN (Bitfield-Mask: 0x01)                  */
#define EPWM_OUT_CR_CH2_P_FORCE_O_Pos     (11UL)                    /*!< CH2_P_FORCE_O (Bit 11)                                */
#define EPWM_OUT_CR_CH2_P_FORCE_O_Msk     (0x800UL)                 /*!< CH2_P_FORCE_O (Bitfield-Mask: 0x01)                   */
#define EPWM_OUT_CR_CH2_N_FORCE_O_Pos     (10UL)                    /*!< CH2_N_FORCE_O (Bit 10)                                */
#define EPWM_OUT_CR_CH2_N_FORCE_O_Msk     (0x400UL)                 /*!< CH2_N_FORCE_O (Bitfield-Mask: 0x01)                   */
#define EPWM_OUT_CR_CH2_P_FORCE_EN_Pos    (9UL)                     /*!< CH2_P_FORCE_EN (Bit 9)                                */
#define EPWM_OUT_CR_CH2_P_FORCE_EN_Msk    (0x200UL)                 /*!< CH2_P_FORCE_EN (Bitfield-Mask: 0x01)                  */
#define EPWM_OUT_CR_CH2_N_FORCE_EN_Pos    (8UL)                     /*!< CH2_N_FORCE_EN (Bit 8)                                */
#define EPWM_OUT_CR_CH2_N_FORCE_EN_Msk    (0x100UL)                 /*!< CH2_N_FORCE_EN (Bitfield-Mask: 0x01)                  */
#define EPWM_OUT_CR_CH1_P_FORCE_O_Pos     (7UL)                     /*!< CH1_P_FORCE_O (Bit 7)                                 */
#define EPWM_OUT_CR_CH1_P_FORCE_O_Msk     (0x80UL)                  /*!< CH1_P_FORCE_O (Bitfield-Mask: 0x01)                   */
#define EPWM_OUT_CR_CH1_N_FORCE_O_Pos     (6UL)                     /*!< CH1_N_FORCE_O (Bit 6)                                 */
#define EPWM_OUT_CR_CH1_N_FORCE_O_Msk     (0x40UL)                  /*!< CH1_N_FORCE_O (Bitfield-Mask: 0x01)                   */
#define EPWM_OUT_CR_CH1_P_FORCE_EN_Pos    (5UL)                     /*!< CH1_P_FORCE_EN (Bit 5)                                */
#define EPWM_OUT_CR_CH1_P_FORCE_EN_Msk    (0x20UL)                  /*!< CH1_P_FORCE_EN (Bitfield-Mask: 0x01)                  */
#define EPWM_OUT_CR_CH1_N_FORCE_EN_Pos    (4UL)                     /*!< CH1_N_FORCE_EN (Bit 4)                                */
#define EPWM_OUT_CR_CH1_N_FORCE_EN_Msk    (0x10UL)                  /*!< CH1_N_FORCE_EN (Bitfield-Mask: 0x01)                  */
#define EPWM_OUT_CR_CH0_P_FORCE_O_Pos     (3UL)                     /*!< CH0_P_FORCE_O (Bit 3)                                 */
#define EPWM_OUT_CR_CH0_P_FORCE_O_Msk     (0x8UL)                   /*!< CH0_P_FORCE_O (Bitfield-Mask: 0x01)                   */
#define EPWM_OUT_CR_CH0_N_FORCE_O_Pos     (2UL)                     /*!< CH0_N_FORCE_O (Bit 2)                                 */
#define EPWM_OUT_CR_CH0_N_FORCE_O_Msk     (0x4UL)                   /*!< CH0_N_FORCE_O (Bitfield-Mask: 0x01)                   */
#define EPWM_OUT_CR_CH0_P_FORCE_EN_Pos    (1UL)                     /*!< CH0_P_FORCE_EN (Bit 1)                                */
#define EPWM_OUT_CR_CH0_P_FORCE_EN_Msk    (0x2UL)                   /*!< CH0_P_FORCE_EN (Bitfield-Mask: 0x01)                  */
#define EPWM_OUT_CR_CH0_N_FORCE_EN_Pos    (0UL)                     /*!< CH0_N_FORCE_EN (Bit 0)                                */
#define EPWM_OUT_CR_CH0_N_FORCE_EN_Msk    (0x1UL)                   /*!< CH0_N_FORCE_EN (Bitfield-Mask: 0x01)                  */
/* =========================================================  DT_CR  ========================================================= */
#define EPWM_DT_CR_DT_LEN_Pos             (0UL)                     /*!< DT_LEN (Bit 0)                                        */
#define EPWM_DT_CR_DT_LEN_Msk             (0x3ffUL)                 /*!< DT_LEN (Bitfield-Mask: 0x3ff)                         */
/* ========================================================  STOP_CR  ======================================================== */
#define EPWM_STOP_CR_CH3_P_STOP_O_Pos     (23UL)                    /*!< CH3_P_STOP_O (Bit 23)                                 */
#define EPWM_STOP_CR_CH3_P_STOP_O_Msk     (0x800000UL)              /*!< CH3_P_STOP_O (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_CH3_N_STOP_O_Pos     (22UL)                    /*!< CH3_N_STOP_O (Bit 22)                                 */
#define EPWM_STOP_CR_CH3_N_STOP_O_Msk     (0x400000UL)              /*!< CH3_N_STOP_O (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_CH2_P_STOP_O_Pos     (21UL)                    /*!< CH2_P_STOP_O (Bit 21)                                 */
#define EPWM_STOP_CR_CH2_P_STOP_O_Msk     (0x200000UL)              /*!< CH2_P_STOP_O (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_CH2_N_STOP_O_Pos     (20UL)                    /*!< CH2_N_STOP_O (Bit 20)                                 */
#define EPWM_STOP_CR_CH2_N_STOP_O_Msk     (0x100000UL)              /*!< CH2_N_STOP_O (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_CH1_P_STOP_O_Pos     (19UL)                    /*!< CH1_P_STOP_O (Bit 19)                                 */
#define EPWM_STOP_CR_CH1_P_STOP_O_Msk     (0x80000UL)               /*!< CH1_P_STOP_O (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_CH1_N_STOP_O_Pos     (18UL)                    /*!< CH1_N_STOP_O (Bit 18)                                 */
#define EPWM_STOP_CR_CH1_N_STOP_O_Msk     (0x40000UL)               /*!< CH1_N_STOP_O (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_CH0_P_STOP_O_Pos     (17UL)                    /*!< CH0_P_STOP_O (Bit 17)                                 */
#define EPWM_STOP_CR_CH0_P_STOP_O_Msk     (0x20000UL)               /*!< CH0_P_STOP_O (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_CH0_N_STOP_O_Pos     (16UL)                    /*!< CH0_N_STOP_O (Bit 16)                                 */
#define EPWM_STOP_CR_CH0_N_STOP_O_Msk     (0x10000UL)               /*!< CH0_N_STOP_O (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_DBG_STOP_EN_Pos      (14UL)                    /*!< DBG_STOP_EN (Bit 14)                                  */
#define EPWM_STOP_CR_DBG_STOP_EN_Msk      (0x4000UL)                /*!< DBG_STOP_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_STOP_CR_ACMP_SEL_Pos         (12UL)                    /*!< ACMP_SEL (Bit 12)                                     */
#define EPWM_STOP_CR_ACMP_SEL_Msk         (0x3000UL)                /*!< ACMP_SEL (Bitfield-Mask: 0x03)                        */
#define EPWM_STOP_CR_ACMP_POL_SEL_Pos     (11UL)                    /*!< ACMP_POL_SEL (Bit 11)                                 */
#define EPWM_STOP_CR_ACMP_POL_SEL_Msk     (0x800UL)                 /*!< ACMP_POL_SEL (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_ACMP_STOP_EN_Pos     (10UL)                    /*!< ACMP_STOP_EN (Bit 10)                                 */
#define EPWM_STOP_CR_ACMP_STOP_EN_Msk     (0x400UL)                 /*!< ACMP_STOP_EN (Bitfield-Mask: 0x01)                    */
#define EPWM_STOP_CR_EXT_POL_SEL_Pos      (9UL)                     /*!< EXT_POL_SEL (Bit 9)                                   */
#define EPWM_STOP_CR_EXT_POL_SEL_Msk      (0x200UL)                 /*!< EXT_POL_SEL (Bitfield-Mask: 0x01)                     */
#define EPWM_STOP_CR_EXT_STOP_EN_Pos      (8UL)                     /*!< EXT_STOP_EN (Bit 8)                                   */
#define EPWM_STOP_CR_EXT_STOP_EN_Msk      (0x100UL)                 /*!< EXT_STOP_EN (Bitfield-Mask: 0x01)                     */
#define EPWM_STOP_CR_FLT_LEN_Pos          (2UL)                     /*!< FLT_LEN (Bit 2)                                       */
#define EPWM_STOP_CR_FLT_LEN_Msk          (0xcUL)                   /*!< FLT_LEN (Bitfield-Mask: 0x03)                         */
#define EPWM_STOP_CR_FLT_SAMPLE_Pos       (0UL)                     /*!< FLT_SAMPLE (Bit 0)                                    */
#define EPWM_STOP_CR_FLT_SAMPLE_Msk       (0x3UL)                   /*!< FLT_SAMPLE (Bitfield-Mask: 0x03)                      */
/* ========================================================  STOP_SR  ======================================================== */
#define EPWM_STOP_SR_ACMP_TRIG_Pos        (2UL)                     /*!< ACMP_TRIG (Bit 2)                                     */
#define EPWM_STOP_SR_ACMP_TRIG_Msk        (0x4UL)                   /*!< ACMP_TRIG (Bitfield-Mask: 0x01)                       */
#define EPWM_STOP_SR_EXT_TRIG_Pos         (1UL)                     /*!< EXT_TRIG (Bit 1)                                      */
#define EPWM_STOP_SR_EXT_TRIG_Msk         (0x2UL)                   /*!< EXT_TRIG (Bitfield-Mask: 0x01)                        */
#define EPWM_STOP_SR_STOP_Pos             (0UL)                     /*!< STOP (Bit 0)                                          */
#define EPWM_STOP_SR_STOP_Msk             (0x1UL)                   /*!< STOP (Bitfield-Mask: 0x01)                            */
/* =========================================================  LOCK  ========================================================== */
#define EPWM_LOCK_KEY_Pos                 (16UL)                    /*!< KEY (Bit 16)                                          */
#define EPWM_LOCK_KEY_Msk                 (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define EPWM_LOCK_VAL_Pos                 (0UL)                     /*!< VAL (Bit 0)                                           */
#define EPWM_LOCK_VAL_Msk                 (0x1UL)                   /*!< VAL (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                            WDG                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CSR  ========================================================== */
#define WDG_CSR_M_VAL_Pos                 (16UL)                    /*!< M_VAL (Bit 16)                                        */
#define WDG_CSR_M_VAL_Msk                 (0xffff0000UL)            /*!< M_VAL (Bitfield-Mask: 0xffff)                         */
#define WDG_CSR_MODE_Pos                  (4UL)                     /*!< MODE (Bit 4)                                          */
#define WDG_CSR_MODE_Msk                  (0xf0UL)                  /*!< MODE (Bitfield-Mask: 0x0f)                            */
#define WDG_CSR_IF_Pos                    (2UL)                     /*!< IF (Bit 2)                                            */
#define WDG_CSR_IF_Msk                    (0x4UL)                   /*!< IF (Bitfield-Mask: 0x01)                              */
#define WDG_CSR_IE_Pos                    (1UL)                     /*!< IE (Bit 1)                                            */
#define WDG_CSR_IE_Msk                    (0x2UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
#define WDG_CSR_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define WDG_CSR_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CLR  ========================================================== */
#define WDG_CLR_CLR_WDG_Pos               (0UL)                     /*!< CLR_WDG (Bit 0)                                       */
#define WDG_CLR_CLR_WDG_Msk               (0xffffffffUL)            /*!< CLR_WDG (Bitfield-Mask: 0xffffffff)                   */


/* =========================================================================================================================== */
/* ================                                           POSIF                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define POSIF_CR_IN2_FLT_LEN_Pos          (29UL)                    /*!< IN2_FLT_LEN (Bit 29)                                  */
#define POSIF_CR_IN2_FLT_LEN_Msk          (0x60000000UL)            /*!< IN2_FLT_LEN (Bitfield-Mask: 0x03)                     */
#define POSIF_CR_IN2_FLT_SAMPLE_Pos       (27UL)                    /*!< IN2_FLT_SAMPLE (Bit 27)                               */
#define POSIF_CR_IN2_FLT_SAMPLE_Msk       (0x18000000UL)            /*!< IN2_FLT_SAMPLE (Bitfield-Mask: 0x03)                  */
#define POSIF_CR_IN2_ACMP_SEL_Pos         (25UL)                    /*!< IN2_ACMP_SEL (Bit 25)                                 */
#define POSIF_CR_IN2_ACMP_SEL_Msk         (0x6000000UL)             /*!< IN2_ACMP_SEL (Bitfield-Mask: 0x03)                    */
#define POSIF_CR_IN2_SEL_Pos              (24UL)                    /*!< IN2_SEL (Bit 24)                                      */
#define POSIF_CR_IN2_SEL_Msk              (0x1000000UL)             /*!< IN2_SEL (Bitfield-Mask: 0x01)                         */
#define POSIF_CR_IN1_FLT_LEN_Pos          (21UL)                    /*!< IN1_FLT_LEN (Bit 21)                                  */
#define POSIF_CR_IN1_FLT_LEN_Msk          (0x600000UL)              /*!< IN1_FLT_LEN (Bitfield-Mask: 0x03)                     */
#define POSIF_CR_IN1_FLT_SAMPLE_Pos       (19UL)                    /*!< IN1_FLT_SAMPLE (Bit 19)                               */
#define POSIF_CR_IN1_FLT_SAMPLE_Msk       (0x180000UL)              /*!< IN1_FLT_SAMPLE (Bitfield-Mask: 0x03)                  */
#define POSIF_CR_IN1_ACMP_SEL_Pos         (17UL)                    /*!< IN1_ACMP_SEL (Bit 17)                                 */
#define POSIF_CR_IN1_ACMP_SEL_Msk         (0x60000UL)               /*!< IN1_ACMP_SEL (Bitfield-Mask: 0x03)                    */
#define POSIF_CR_IN1_SEL_Pos              (16UL)                    /*!< IN1_SEL (Bit 16)                                      */
#define POSIF_CR_IN1_SEL_Msk              (0x10000UL)               /*!< IN1_SEL (Bitfield-Mask: 0x01)                         */
#define POSIF_CR_IN0_FLT_LEN_Pos          (13UL)                    /*!< IN0_FLT_LEN (Bit 13)                                  */
#define POSIF_CR_IN0_FLT_LEN_Msk          (0x6000UL)                /*!< IN0_FLT_LEN (Bitfield-Mask: 0x03)                     */
#define POSIF_CR_IN0_FLT_SAMPLE_Pos       (11UL)                    /*!< IN0_FLT_SAMPLE (Bit 11)                               */
#define POSIF_CR_IN0_FLT_SAMPLE_Msk       (0x1800UL)                /*!< IN0_FLT_SAMPLE (Bitfield-Mask: 0x03)                  */
#define POSIF_CR_IN0_ACMP_SEL_Pos         (9UL)                     /*!< IN0_ACMP_SEL (Bit 9)                                  */
#define POSIF_CR_IN0_ACMP_SEL_Msk         (0x600UL)                 /*!< IN0_ACMP_SEL (Bitfield-Mask: 0x03)                    */
#define POSIF_CR_IN0_SEL_Pos              (8UL)                     /*!< IN0_SEL (Bit 8)                                       */
#define POSIF_CR_IN0_SEL_Msk              (0x100UL)                 /*!< IN0_SEL (Bitfield-Mask: 0x01)                         */
#define POSIF_CR_CLK_DIV_Pos              (2UL)                     /*!< CLK_DIV (Bit 2)                                       */
#define POSIF_CR_CLK_DIV_Msk              (0x1cUL)                  /*!< CLK_DIV (Bitfield-Mask: 0x07)                         */
#define POSIF_CR_MODE_Pos                 (1UL)                     /*!< MODE (Bit 1)                                          */
#define POSIF_CR_MODE_Msk                 (0x2UL)                   /*!< MODE (Bitfield-Mask: 0x01)                            */
#define POSIF_CR_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define POSIF_CR_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ========================================================  ENC_CR  ========================================================= */
#define POSIF_ENC_CR_PULSE_CNT_OF_IE_Pos  (7UL)                     /*!< PULSE_CNT_OF_IE (Bit 7)                               */
#define POSIF_ENC_CR_PULSE_CNT_OF_IE_Msk  (0x80UL)                  /*!< PULSE_CNT_OF_IE (Bitfield-Mask: 0x01)                 */
#define POSIF_ENC_CR_MAX_POS_IE_Pos       (6UL)                     /*!< MAX_POS_IE (Bit 6)                                    */
#define POSIF_ENC_CR_MAX_POS_IE_Msk       (0x40UL)                  /*!< MAX_POS_IE (Bitfield-Mask: 0x01)                      */
#define POSIF_ENC_CR_ZIN_ACTION_Pos       (5UL)                     /*!< ZIN_ACTION (Bit 5)                                    */
#define POSIF_ENC_CR_ZIN_ACTION_Msk       (0x20UL)                  /*!< ZIN_ACTION (Bitfield-Mask: 0x01)                      */
#define POSIF_ENC_CR_ZIN_EN_Pos           (4UL)                     /*!< ZIN_EN (Bit 4)                                        */
#define POSIF_ENC_CR_ZIN_EN_Msk           (0x10UL)                  /*!< ZIN_EN (Bitfield-Mask: 0x01)                          */
#define POSIF_ENC_CR_PULSE_CNT_EN_Pos     (3UL)                     /*!< PULSE_CNT_EN (Bit 3)                                  */
#define POSIF_ENC_CR_PULSE_CNT_EN_Msk     (0x8UL)                   /*!< PULSE_CNT_EN (Bitfield-Mask: 0x01)                    */
#define POSIF_ENC_CR_ENC_MODE_Pos         (0UL)                     /*!< ENC_MODE (Bit 0)                                      */
#define POSIF_ENC_CR_ENC_MODE_Msk         (0x7UL)                   /*!< ENC_MODE (Bitfield-Mask: 0x07)                        */
/* ========================================================  ENC_SR  ========================================================= */
#define POSIF_ENC_SR_ENC_DIR_Pos          (2UL)                     /*!< ENC_DIR (Bit 2)                                       */
#define POSIF_ENC_SR_ENC_DIR_Msk          (0x4UL)                   /*!< ENC_DIR (Bitfield-Mask: 0x01)                         */
#define POSIF_ENC_SR_PULSE_CNT_OF_IF_Pos  (1UL)                     /*!< PULSE_CNT_OF_IF (Bit 1)                               */
#define POSIF_ENC_SR_PULSE_CNT_OF_IF_Msk  (0x2UL)                   /*!< PULSE_CNT_OF_IF (Bitfield-Mask: 0x01)                 */
#define POSIF_ENC_SR_MAX_POS_IF_Pos       (0UL)                     /*!< MAX_POS_IF (Bit 0)                                    */
#define POSIF_ENC_SR_MAX_POS_IF_Msk       (0x1UL)                   /*!< MAX_POS_IF (Bitfield-Mask: 0x01)                      */
/* ======================================================  ENC_MAX_POS  ====================================================== */
#define POSIF_ENC_MAX_POS_MAX_POS_Pos     (0UL)                     /*!< MAX_POS (Bit 0)                                       */
#define POSIF_ENC_MAX_POS_MAX_POS_Msk     (0xffffUL)                /*!< MAX_POS (Bitfield-Mask: 0xffff)                       */
/* ======================================================  ENC_CUR_POS  ====================================================== */
#define POSIF_ENC_CUR_POS_CUR_POS_Pos     (0UL)                     /*!< CUR_POS (Bit 0)                                       */
#define POSIF_ENC_CUR_POS_CUR_POS_Msk     (0xffffUL)                /*!< CUR_POS (Bitfield-Mask: 0xffff)                       */
/* =====================================================  ENC_PULSE_CNT  ===================================================== */
#define POSIF_ENC_PULSE_CNT_CNT_Pos       (0UL)                     /*!< CNT (Bit 0)                                           */
#define POSIF_ENC_PULSE_CNT_CNT_Msk       (0xffffffUL)              /*!< CNT (Bitfield-Mask: 0xffffff)                         */
/* ========================================================  HALL_CR  ======================================================== */
#define POSIF_HALL_CR_UPDATE_IE_Pos       (1UL)                     /*!< UPDATE_IE (Bit 1)                                     */
#define POSIF_HALL_CR_UPDATE_IE_Msk       (0x2UL)                   /*!< UPDATE_IE (Bitfield-Mask: 0x01)                       */
#define POSIF_HALL_CR_MAX_WIDTH_IE_Pos    (0UL)                     /*!< MAX_WIDTH_IE (Bit 0)                                  */
#define POSIF_HALL_CR_MAX_WIDTH_IE_Msk    (0x1UL)                   /*!< MAX_WIDTH_IE (Bitfield-Mask: 0x01)                    */
/* ========================================================  HALL_SR  ======================================================== */
#define POSIF_HALL_SR_UPDATE_IF_Pos       (7UL)                     /*!< UPDATE_IF (Bit 7)                                     */
#define POSIF_HALL_SR_UPDATE_IF_Msk       (0x80UL)                  /*!< UPDATE_IF (Bitfield-Mask: 0x01)                       */
#define POSIF_HALL_SR_MAX_WIDTH_IF_Pos    (6UL)                     /*!< MAX_WIDTH_IF (Bit 6)                                  */
#define POSIF_HALL_SR_MAX_WIDTH_IF_Msk    (0x40UL)                  /*!< MAX_WIDTH_IF (Bitfield-Mask: 0x01)                    */
#define POSIF_HALL_SR_RAW_Pos             (3UL)                     /*!< RAW (Bit 3)                                           */
#define POSIF_HALL_SR_RAW_Msk             (0x38UL)                  /*!< RAW (Bitfield-Mask: 0x07)                             */
#define POSIF_HALL_SR_DATA_Pos            (0UL)                     /*!< DATA (Bit 0)                                          */
#define POSIF_HALL_SR_DATA_Msk            (0x7UL)                   /*!< DATA (Bitfield-Mask: 0x07)                            */
/* ======================================================  HALL_WIDTH  ======================================================= */
#define POSIF_HALL_WIDTH_HALL_WIDTH_Pos   (0UL)                     /*!< HALL_WIDTH (Bit 0)                                    */
#define POSIF_HALL_WIDTH_HALL_WIDTH_Msk   (0xffffffUL)              /*!< HALL_WIDTH (Bitfield-Mask: 0xffffff)                  */
/* ====================================================  HALL_MAX_WIDTH  ===================================================== */
#define POSIF_HALL_MAX_WIDTH_MAX_WIDTH_Pos (0UL)                    /*!< MAX_WIDTH (Bit 0)                                     */
#define POSIF_HALL_MAX_WIDTH_MAX_WIDTH_Msk (0xffffffUL)             /*!< MAX_WIDTH (Bitfield-Mask: 0xffffff)                   */
/* ======================================================  HALL_DELAY  ======================================================= */
#define POSIF_HALL_DELAY_VAL_Pos          (0UL)                     /*!< VAL (Bit 0)                                           */
#define POSIF_HALL_DELAY_VAL_Msk          (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */


/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  SR  =========================================================== */
#define DMA_SR_CH4_STATUS_Pos             (18UL)                    /*!< CH4_STATUS (Bit 18)                                   */
#define DMA_SR_CH4_STATUS_Msk             (0xc0000UL)               /*!< CH4_STATUS (Bitfield-Mask: 0x03)                      */
#define DMA_SR_CH4_ERR_IF_Pos             (17UL)                    /*!< CH4_ERR_IF (Bit 17)                                   */
#define DMA_SR_CH4_ERR_IF_Msk             (0x20000UL)               /*!< CH4_ERR_IF (Bitfield-Mask: 0x01)                      */
#define DMA_SR_CH4_FIS_IF_Pos             (16UL)                    /*!< CH4_FIS_IF (Bit 16)                                   */
#define DMA_SR_CH4_FIS_IF_Msk             (0x10000UL)               /*!< CH4_FIS_IF (Bitfield-Mask: 0x01)                      */
#define DMA_SR_CH3_STATUS_Pos             (14UL)                    /*!< CH3_STATUS (Bit 14)                                   */
#define DMA_SR_CH3_STATUS_Msk             (0xc000UL)                /*!< CH3_STATUS (Bitfield-Mask: 0x03)                      */
#define DMA_SR_CH3_ERR_IF_Pos             (13UL)                    /*!< CH3_ERR_IF (Bit 13)                                   */
#define DMA_SR_CH3_ERR_IF_Msk             (0x2000UL)                /*!< CH3_ERR_IF (Bitfield-Mask: 0x01)                      */
#define DMA_SR_CH3_FIS_IF_Pos             (12UL)                    /*!< CH3_FIS_IF (Bit 12)                                   */
#define DMA_SR_CH3_FIS_IF_Msk             (0x1000UL)                /*!< CH3_FIS_IF (Bitfield-Mask: 0x01)                      */
#define DMA_SR_CH2_STATUS_Pos             (10UL)                    /*!< CH2_STATUS (Bit 10)                                   */
#define DMA_SR_CH2_STATUS_Msk             (0xc00UL)                 /*!< CH2_STATUS (Bitfield-Mask: 0x03)                      */
#define DMA_SR_CH2_ERR_IF_Pos             (9UL)                     /*!< CH2_ERR_IF (Bit 9)                                    */
#define DMA_SR_CH2_ERR_IF_Msk             (0x200UL)                 /*!< CH2_ERR_IF (Bitfield-Mask: 0x01)                      */
#define DMA_SR_CH2_FIS_IF_Pos             (8UL)                     /*!< CH2_FIS_IF (Bit 8)                                    */
#define DMA_SR_CH2_FIS_IF_Msk             (0x100UL)                 /*!< CH2_FIS_IF (Bitfield-Mask: 0x01)                      */
#define DMA_SR_CH1_STATUS_Pos             (6UL)                     /*!< CH1_STATUS (Bit 6)                                    */
#define DMA_SR_CH1_STATUS_Msk             (0xc0UL)                  /*!< CH1_STATUS (Bitfield-Mask: 0x03)                      */
#define DMA_SR_CH1_ERR_IF_Pos             (5UL)                     /*!< CH1_ERR_IF (Bit 5)                                    */
#define DMA_SR_CH1_ERR_IF_Msk             (0x20UL)                  /*!< CH1_ERR_IF (Bitfield-Mask: 0x01)                      */
#define DMA_SR_CH1_FIS_IF_Pos             (4UL)                     /*!< CH1_FIS_IF (Bit 4)                                    */
#define DMA_SR_CH1_FIS_IF_Msk             (0x10UL)                  /*!< CH1_FIS_IF (Bitfield-Mask: 0x01)                      */
#define DMA_SR_CH0_STATUS_Pos             (2UL)                     /*!< CH0_STATUS (Bit 2)                                    */
#define DMA_SR_CH0_STATUS_Msk             (0xcUL)                   /*!< CH0_STATUS (Bitfield-Mask: 0x03)                      */
#define DMA_SR_CH0_ERR_IF_Pos             (1UL)                     /*!< CH0_ERR_IF (Bit 1)                                    */
#define DMA_SR_CH0_ERR_IF_Msk             (0x2UL)                   /*!< CH0_ERR_IF (Bitfield-Mask: 0x01)                      */
#define DMA_SR_CH0_FIS_IF_Pos             (0UL)                     /*!< CH0_FIS_IF (Bit 0)                                    */
#define DMA_SR_CH0_FIS_IF_Msk             (0x1UL)                   /*!< CH0_FIS_IF (Bitfield-Mask: 0x01)                      */
/* =======================================================  CH0_CFG0  ======================================================== */
#define DMA_CH0_CFG0_REQ_SEL_Pos          (8UL)                     /*!< REQ_SEL (Bit 8)                                       */
#define DMA_CH0_CFG0_REQ_SEL_Msk          (0x1f00UL)                /*!< REQ_SEL (Bitfield-Mask: 0x1f)                         */
#define DMA_CH0_CFG0_ERR_IE_Pos           (4UL)                     /*!< ERR_IE (Bit 4)                                        */
#define DMA_CH0_CFG0_ERR_IE_Msk           (0x10UL)                  /*!< ERR_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH0_CFG0_FIS_IE_Pos           (3UL)                     /*!< FIS_IE (Bit 3)                                        */
#define DMA_CH0_CFG0_FIS_IE_Msk           (0x8UL)                   /*!< FIS_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH0_CFG0_SW_TRIG_Pos          (2UL)                     /*!< SW_TRIG (Bit 2)                                       */
#define DMA_CH0_CFG0_SW_TRIG_Msk          (0x4UL)                   /*!< SW_TRIG (Bitfield-Mask: 0x01)                         */
#define DMA_CH0_CFG0_CIRC_Pos             (1UL)                     /*!< CIRC (Bit 1)                                          */
#define DMA_CH0_CFG0_CIRC_Msk             (0x2UL)                   /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CH0_CFG0_EN_Pos               (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CH0_CFG0_EN_Msk               (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  CH0_CFG1  ======================================================== */
#define DMA_CH0_CFG1_ROUND_NUM_Pos        (20UL)                    /*!< ROUND_NUM (Bit 20)                                    */
#define DMA_CH0_CFG1_ROUND_NUM_Msk        (0xfff00000UL)            /*!< ROUND_NUM (Bitfield-Mask: 0xfff)                      */
#define DMA_CH0_CFG1_DST_INC_MODE_Pos     (19UL)                    /*!< DST_INC_MODE (Bit 19)                                 */
#define DMA_CH0_CFG1_DST_INC_MODE_Msk     (0x80000UL)               /*!< DST_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH0_CFG1_SRC_INC_MODE_Pos     (18UL)                    /*!< SRC_INC_MODE (Bit 18)                                 */
#define DMA_CH0_CFG1_SRC_INC_MODE_Msk     (0x40000UL)               /*!< SRC_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH0_CFG1_DATA_SIZE_Pos        (16UL)                    /*!< DATA_SIZE (Bit 16)                                    */
#define DMA_CH0_CFG1_DATA_SIZE_Msk        (0x30000UL)               /*!< DATA_SIZE (Bitfield-Mask: 0x03)                       */
#define DMA_CH0_CFG1_DATA_NUM_Pos         (0UL)                     /*!< DATA_NUM (Bit 0)                                      */
#define DMA_CH0_CFG1_DATA_NUM_Msk         (0xffffUL)                /*!< DATA_NUM (Bitfield-Mask: 0xffff)                      */
/* =====================================================  CH0_SRC_ADDR  ====================================================== */
#define DMA_CH0_SRC_ADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_CH0_SRC_ADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  CH0_DST_ADDR  ====================================================== */
#define DMA_CH0_DST_ADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_CH0_DST_ADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  CH1_CFG0  ======================================================== */
#define DMA_CH1_CFG0_REQ_SEL_Pos          (8UL)                     /*!< REQ_SEL (Bit 8)                                       */
#define DMA_CH1_CFG0_REQ_SEL_Msk          (0x1f00UL)                /*!< REQ_SEL (Bitfield-Mask: 0x1f)                         */
#define DMA_CH1_CFG0_ERR_IE_Pos           (4UL)                     /*!< ERR_IE (Bit 4)                                        */
#define DMA_CH1_CFG0_ERR_IE_Msk           (0x10UL)                  /*!< ERR_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH1_CFG0_FIS_IE_Pos           (3UL)                     /*!< FIS_IE (Bit 3)                                        */
#define DMA_CH1_CFG0_FIS_IE_Msk           (0x8UL)                   /*!< FIS_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH1_CFG0_SW_TRIG_Pos          (2UL)                     /*!< SW_TRIG (Bit 2)                                       */
#define DMA_CH1_CFG0_SW_TRIG_Msk          (0x4UL)                   /*!< SW_TRIG (Bitfield-Mask: 0x01)                         */
#define DMA_CH1_CFG0_CIRC_Pos             (1UL)                     /*!< CIRC (Bit 1)                                          */
#define DMA_CH1_CFG0_CIRC_Msk             (0x2UL)                   /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CH1_CFG0_EN_Pos               (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CH1_CFG0_EN_Msk               (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  CH1_CFG1  ======================================================== */
#define DMA_CH1_CFG1_ROUND_NUM_Pos        (20UL)                    /*!< ROUND_NUM (Bit 20)                                    */
#define DMA_CH1_CFG1_ROUND_NUM_Msk        (0xfff00000UL)            /*!< ROUND_NUM (Bitfield-Mask: 0xfff)                      */
#define DMA_CH1_CFG1_DST_INC_MODE_Pos     (19UL)                    /*!< DST_INC_MODE (Bit 19)                                 */
#define DMA_CH1_CFG1_DST_INC_MODE_Msk     (0x80000UL)               /*!< DST_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH1_CFG1_SRC_INC_MODE_Pos     (18UL)                    /*!< SRC_INC_MODE (Bit 18)                                 */
#define DMA_CH1_CFG1_SRC_INC_MODE_Msk     (0x40000UL)               /*!< SRC_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH1_CFG1_DATA_SIZE_Pos        (16UL)                    /*!< DATA_SIZE (Bit 16)                                    */
#define DMA_CH1_CFG1_DATA_SIZE_Msk        (0x30000UL)               /*!< DATA_SIZE (Bitfield-Mask: 0x03)                       */
#define DMA_CH1_CFG1_DATA_NUM_Pos         (0UL)                     /*!< DATA_NUM (Bit 0)                                      */
#define DMA_CH1_CFG1_DATA_NUM_Msk         (0xffffUL)                /*!< DATA_NUM (Bitfield-Mask: 0xffff)                      */
/* =====================================================  CH1_SRC_ADDR  ====================================================== */
#define DMA_CH1_SRC_ADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_CH1_SRC_ADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  CH1_DST_ADDR  ====================================================== */
#define DMA_CH1_DST_ADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_CH1_DST_ADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  CH2_CFG0  ======================================================== */
#define DMA_CH2_CFG0_REQ_SEL_Pos          (8UL)                     /*!< REQ_SEL (Bit 8)                                       */
#define DMA_CH2_CFG0_REQ_SEL_Msk          (0x1f00UL)                /*!< REQ_SEL (Bitfield-Mask: 0x1f)                         */
#define DMA_CH2_CFG0_ERR_IE_Pos           (4UL)                     /*!< ERR_IE (Bit 4)                                        */
#define DMA_CH2_CFG0_ERR_IE_Msk           (0x10UL)                  /*!< ERR_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH2_CFG0_FIS_IE_Pos           (3UL)                     /*!< FIS_IE (Bit 3)                                        */
#define DMA_CH2_CFG0_FIS_IE_Msk           (0x8UL)                   /*!< FIS_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH2_CFG0_SW_TRIG_Pos          (2UL)                     /*!< SW_TRIG (Bit 2)                                       */
#define DMA_CH2_CFG0_SW_TRIG_Msk          (0x4UL)                   /*!< SW_TRIG (Bitfield-Mask: 0x01)                         */
#define DMA_CH2_CFG0_CIRC_Pos             (1UL)                     /*!< CIRC (Bit 1)                                          */
#define DMA_CH2_CFG0_CIRC_Msk             (0x2UL)                   /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CH2_CFG0_EN_Pos               (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CH2_CFG0_EN_Msk               (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  CH2_CFG1  ======================================================== */
#define DMA_CH2_CFG1_ROUND_NUM_Pos        (20UL)                    /*!< ROUND_NUM (Bit 20)                                    */
#define DMA_CH2_CFG1_ROUND_NUM_Msk        (0xfff00000UL)            /*!< ROUND_NUM (Bitfield-Mask: 0xfff)                      */
#define DMA_CH2_CFG1_DST_INC_MODE_Pos     (19UL)                    /*!< DST_INC_MODE (Bit 19)                                 */
#define DMA_CH2_CFG1_DST_INC_MODE_Msk     (0x80000UL)               /*!< DST_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH2_CFG1_SRC_INC_MODE_Pos     (18UL)                    /*!< SRC_INC_MODE (Bit 18)                                 */
#define DMA_CH2_CFG1_SRC_INC_MODE_Msk     (0x40000UL)               /*!< SRC_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH2_CFG1_DATA_SIZE_Pos        (16UL)                    /*!< DATA_SIZE (Bit 16)                                    */
#define DMA_CH2_CFG1_DATA_SIZE_Msk        (0x30000UL)               /*!< DATA_SIZE (Bitfield-Mask: 0x03)                       */
#define DMA_CH2_CFG1_DATA_NUM_Pos         (0UL)                     /*!< DATA_NUM (Bit 0)                                      */
#define DMA_CH2_CFG1_DATA_NUM_Msk         (0xffffUL)                /*!< DATA_NUM (Bitfield-Mask: 0xffff)                      */
/* =====================================================  CH2_SRC_ADDR  ====================================================== */
#define DMA_CH2_SRC_ADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_CH2_SRC_ADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  CH2_DST_ADDR  ====================================================== */
#define DMA_CH2_DST_ADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_CH2_DST_ADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  CH3_CFG0  ======================================================== */
#define DMA_CH3_CFG0_REQ_SEL_Pos          (8UL)                     /*!< REQ_SEL (Bit 8)                                       */
#define DMA_CH3_CFG0_REQ_SEL_Msk          (0x1f00UL)                /*!< REQ_SEL (Bitfield-Mask: 0x1f)                         */
#define DMA_CH3_CFG0_ERR_IE_Pos           (4UL)                     /*!< ERR_IE (Bit 4)                                        */
#define DMA_CH3_CFG0_ERR_IE_Msk           (0x10UL)                  /*!< ERR_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH3_CFG0_FIS_IE_Pos           (3UL)                     /*!< FIS_IE (Bit 3)                                        */
#define DMA_CH3_CFG0_FIS_IE_Msk           (0x8UL)                   /*!< FIS_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH3_CFG0_SW_TRIG_Pos          (2UL)                     /*!< SW_TRIG (Bit 2)                                       */
#define DMA_CH3_CFG0_SW_TRIG_Msk          (0x4UL)                   /*!< SW_TRIG (Bitfield-Mask: 0x01)                         */
#define DMA_CH3_CFG0_CIRC_Pos             (1UL)                     /*!< CIRC (Bit 1)                                          */
#define DMA_CH3_CFG0_CIRC_Msk             (0x2UL)                   /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CH3_CFG0_EN_Pos               (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CH3_CFG0_EN_Msk               (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  CH3_CFG1  ======================================================== */
#define DMA_CH3_CFG1_ROUND_NUM_Pos        (20UL)                    /*!< ROUND_NUM (Bit 20)                                    */
#define DMA_CH3_CFG1_ROUND_NUM_Msk        (0xfff00000UL)            /*!< ROUND_NUM (Bitfield-Mask: 0xfff)                      */
#define DMA_CH3_CFG1_DST_INC_MODE_Pos     (19UL)                    /*!< DST_INC_MODE (Bit 19)                                 */
#define DMA_CH3_CFG1_DST_INC_MODE_Msk     (0x80000UL)               /*!< DST_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH3_CFG1_SRC_INC_MODE_Pos     (18UL)                    /*!< SRC_INC_MODE (Bit 18)                                 */
#define DMA_CH3_CFG1_SRC_INC_MODE_Msk     (0x40000UL)               /*!< SRC_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH3_CFG1_DATA_SIZE_Pos        (16UL)                    /*!< DATA_SIZE (Bit 16)                                    */
#define DMA_CH3_CFG1_DATA_SIZE_Msk        (0x30000UL)               /*!< DATA_SIZE (Bitfield-Mask: 0x03)                       */
#define DMA_CH3_CFG1_DATA_NUM_Pos         (0UL)                     /*!< DATA_NUM (Bit 0)                                      */
#define DMA_CH3_CFG1_DATA_NUM_Msk         (0xffffUL)                /*!< DATA_NUM (Bitfield-Mask: 0xffff)                      */
/* =====================================================  CH3_SRC_ADDR  ====================================================== */
#define DMA_CH3_SRC_ADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_CH3_SRC_ADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  CH3_DST_ADDR  ====================================================== */
#define DMA_CH3_DST_ADDR_ADDR_Pos        (0UL)                      /*!< ADDR (Bit 0)                                          */
#define DMA_CH3_DST_ADDR_ADDR_Msk        (0xffffffffUL)             /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  CH4_CFG0  ======================================================== */
#define DMA_CH4_CFG0_REQ_SEL_Pos          (8UL)                     /*!< REQ_SEL (Bit 8)                                       */
#define DMA_CH4_CFG0_REQ_SEL_Msk          (0x1f00UL)                /*!< REQ_SEL (Bitfield-Mask: 0x1f)                         */
#define DMA_CH4_CFG0_ERR_IE_Pos           (4UL)                     /*!< ERR_IE (Bit 4)                                        */
#define DMA_CH4_CFG0_ERR_IE_Msk           (0x10UL)                  /*!< ERR_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH4_CFG0_FIS_IE_Pos           (3UL)                     /*!< FIS_IE (Bit 3)                                        */
#define DMA_CH4_CFG0_FIS_IE_Msk           (0x8UL)                   /*!< FIS_IE (Bitfield-Mask: 0x01)                          */
#define DMA_CH4_CFG0_SW_TRIG_Pos          (2UL)                     /*!< SW_TRIG (Bit 2)                                       */
#define DMA_CH4_CFG0_SW_TRIG_Msk          (0x4UL)                   /*!< SW_TRIG (Bitfield-Mask: 0x01)                         */
#define DMA_CH4_CFG0_CIRC_Pos             (1UL)                     /*!< CIRC (Bit 1)                                          */
#define DMA_CH4_CFG0_CIRC_Msk             (0x2UL)                   /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CH4_CFG0_EN_Pos               (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CH4_CFG0_EN_Msk               (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  CH4_CFG1  ======================================================== */
#define DMA_CH4_CFG1_ROUND_NUM_Pos        (20UL)                    /*!< ROUND_NUM (Bit 20)                                    */
#define DMA_CH4_CFG1_ROUND_NUM_Msk        (0xfff00000UL)            /*!< ROUND_NUM (Bitfield-Mask: 0xfff)                      */
#define DMA_CH4_CFG1_DST_INC_MODE_Pos     (19UL)                    /*!< DST_INC_MODE (Bit 19)                                 */
#define DMA_CH4_CFG1_DST_INC_MODE_Msk     (0x80000UL)               /*!< DST_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH4_CFG1_SRC_INC_MODE_Pos     (18UL)                    /*!< SRC_INC_MODE (Bit 18)                                 */
#define DMA_CH4_CFG1_SRC_INC_MODE_Msk     (0x40000UL)               /*!< SRC_INC_MODE (Bitfield-Mask: 0x01)                    */
#define DMA_CH4_CFG1_DATA_SIZE_Pos        (16UL)                    /*!< DATA_SIZE (Bit 16)                                    */
#define DMA_CH4_CFG1_DATA_SIZE_Msk        (0x30000UL)               /*!< DATA_SIZE (Bitfield-Mask: 0x03)                       */
#define DMA_CH4_CFG1_DATA_NUM_Pos         (0UL)                     /*!< DATA_NUM (Bit 0)                                      */
#define DMA_CH4_CFG1_DATA_NUM_Msk         (0xffffUL)                /*!< DATA_NUM (Bitfield-Mask: 0xffff)                      */
/* =====================================================  CH4_SRC_ADDR  ====================================================== */
#define DMA_CH4_SRC_ADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_CH4_SRC_ADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  CH4_DST_ADDR  ====================================================== */
#define DMA_CH4_DST_ADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_CH4_DST_ADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */


/* =========================================================================================================================== */
/* ================                                            DSP                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define DSP_CR_DONE_DE_Pos                (31UL)                    /*!< DONE_DE (Bit 31)                                      */
#define DSP_CR_DONE_DE_Msk                (0x80000000UL)            /*!< DONE_DE (Bitfield-Mask: 0x01)                         */
#define DSP_CR_DONE_IE_Pos                (30UL)                    /*!< DONE_IE (Bit 30)                                      */
#define DSP_CR_DONE_IE_Msk                (0x40000000UL)            /*!< DONE_IE (Bitfield-Mask: 0x01)                         */
#define DSP_CR_DMA_TRIG_SEL_Pos           (27UL)                    /*!< DMA_TRIG_SEL (Bit 27)                                 */
#define DSP_CR_DMA_TRIG_SEL_Msk           (0x38000000UL)            /*!< DMA_TRIG_SEL (Bitfield-Mask: 0x07)                    */
#define DSP_CR_DMA_TRIG_EN_Pos            (26UL)                    /*!< DMA_TRIG_EN (Bit 26)                                  */
#define DSP_CR_DMA_TRIG_EN_Msk            (0x4000000UL)             /*!< DMA_TRIG_EN (Bitfield-Mask: 0x01)                     */
#define DSP_CR_EN_Pos                     (25UL)                    /*!< EN (Bit 25)                                           */
#define DSP_CR_EN_Msk                     (0x2000000UL)             /*!< EN (Bitfield-Mask: 0x01)                              */
#define DSP_CR_PC_END_Pos                 (16UL)                    /*!< PC_END (Bit 16)                                       */
#define DSP_CR_PC_END_Msk                 (0x1ff0000UL)             /*!< PC_END (Bitfield-Mask: 0x1ff)                         */
#define DSP_CR_INS_ERR_IE_Pos             (15UL)                    /*!< INS_ERR_IE (Bit 15)                                   */
#define DSP_CR_INS_ERR_IE_Msk             (0x8000UL)                /*!< INS_ERR_IE (Bitfield-Mask: 0x01)                      */
#define DSP_CR_UDR_IE_Pos                 (14UL)                    /*!< UDR_IE (Bit 14)                                       */
#define DSP_CR_UDR_IE_Msk                 (0x4000UL)                /*!< UDR_IE (Bitfield-Mask: 0x01)                          */
#define DSP_CR_DIV_ZERO_IE_Pos            (13UL)                    /*!< DIV_ZERO_IE (Bit 13)                                  */
#define DSP_CR_DIV_ZERO_IE_Msk            (0x2000UL)                /*!< DIV_ZERO_IE (Bitfield-Mask: 0x01)                     */
#define DSP_CR_PC_START_Pos               (0UL)                     /*!< PC_START (Bit 0)                                      */
#define DSP_CR_PC_START_Msk               (0x1ffUL)                 /*!< PC_START (Bitfield-Mask: 0x1ff)                       */
/* =========================================================  START  ========================================================= */
#define DSP_START_START_Pos               (0UL)                     /*!< START (Bit 0)                                         */
#define DSP_START_START_Msk               (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SR  =========================================================== */
#define DSP_SR_INS_ERR_IF_Pos             (22UL)                    /*!< INS_ERR_IF (Bit 22)                                   */
#define DSP_SR_INS_ERR_IF_Msk             (0x400000UL)              /*!< INS_ERR_IF (Bitfield-Mask: 0x01)                      */
#define DSP_SR_UDR_IF_Pos                 (21UL)                    /*!< UDR_IF (Bit 21)                                       */
#define DSP_SR_UDR_IF_Msk                 (0x200000UL)              /*!< UDR_IF (Bitfield-Mask: 0x01)                          */
#define DSP_SR_BREAK_POINT_IF_Pos         (20UL)                    /*!< BREAK_POINT_IF (Bit 20)                               */
#define DSP_SR_BREAK_POINT_IF_Msk         (0x100000UL)              /*!< BREAK_POINT_IF (Bitfield-Mask: 0x01)                  */
#define DSP_SR_EWDG_IF_Pos                (19UL)                    /*!< EWDG_IF (Bit 19)                                      */
#define DSP_SR_EWDG_IF_Msk                (0x80000UL)               /*!< EWDG_IF (Bitfield-Mask: 0x01)                         */
#define DSP_SR_DONE_IF_Pos                (18UL)                    /*!< DONE_IF (Bit 18)                                      */
#define DSP_SR_DONE_IF_Msk                (0x40000UL)               /*!< DONE_IF (Bitfield-Mask: 0x01)                         */
#define DSP_SR_DIV_ZERO_IF_Pos            (17UL)                    /*!< DIV_ZERO_IF (Bit 17)                                  */
#define DSP_SR_DIV_ZERO_IF_Msk            (0x20000UL)               /*!< DIV_ZERO_IF (Bitfield-Mask: 0x01)                     */
#define DSP_SR_BUSY_Pos                   (16UL)                    /*!< BUSY (Bit 16)                                         */
#define DSP_SR_BUSY_Msk                   (0x10000UL)               /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define DSP_SR_PC_Pos                     (0UL)                     /*!< PC (Bit 0)                                            */
#define DSP_SR_PC_Msk                     (0x1ffUL)                 /*!< PC (Bitfield-Mask: 0x1ff)                             */
/* =========================================================  EWDG  ========================================================== */
#define DSP_EWDG_SYS_RST_EN_Pos           (18UL)                    /*!< SYS_RST_EN (Bit 18)                                   */
#define DSP_EWDG_SYS_RST_EN_Msk           (0x40000UL)               /*!< SYS_RST_EN (Bitfield-Mask: 0x01)                      */
#define DSP_EWDG_EWDG_IE_Pos              (17UL)                    /*!< EWDG_IE (Bit 17)                                      */
#define DSP_EWDG_EWDG_IE_Msk              (0x20000UL)               /*!< EWDG_IE (Bitfield-Mask: 0x01)                         */
#define DSP_EWDG_EWDG_EN_Pos              (16UL)                    /*!< EWDG_EN (Bit 16)                                      */
#define DSP_EWDG_EWDG_EN_Msk              (0x10000UL)               /*!< EWDG_EN (Bitfield-Mask: 0x01)                         */
#define DSP_EWDG_TIM_OUT_VAL_Pos          (0UL)                     /*!< TIM_OUT_VAL (Bit 0)                                   */
#define DSP_EWDG_TIM_OUT_VAL_Msk          (0x3ffUL)                 /*!< TIM_OUT_VAL (Bitfield-Mask: 0x3ff)                    */
/* =========================================================  DEBUG  ========================================================= */
#define DSP_DEBUG_BREAK_POINT_IE_Pos      (17UL)                    /*!< BREAK_POINT_IE (Bit 17)                               */
#define DSP_DEBUG_BREAK_POINT_IE_Msk      (0x20000UL)               /*!< BREAK_POINT_IE (Bitfield-Mask: 0x01)                  */
#define DSP_DEBUG_BREAK_POINT_EN_Pos      (16UL)                    /*!< BREAK_POINT_EN (Bit 16)                               */
#define DSP_DEBUG_BREAK_POINT_EN_Msk      (0x10000UL)               /*!< BREAK_POINT_EN (Bitfield-Mask: 0x01)                  */
#define DSP_DEBUG_BREAK_POINT_Pos         (0UL)                     /*!< BREAK_POINT (Bit 0)                                   */
#define DSP_DEBUG_BREAK_POINT_Msk         (0x1ffUL)                 /*!< BREAK_POINT (Bitfield-Mask: 0x1ff)                    */
/* =========================================================  GPRx  ========================================================== */
#define DSP_GPR_DATA_Pos                  (0UL)                     /*!< DATA (Bit 0)                                          */
#define DSP_GPR_DATA_Msk                  (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  SDRx  ========================================================== */
#define DSP_SDR_DATA_Pos                  (0UL)                     /*!< DATA (Bit 0)                                          */
#define DSP_SDR_DATA_Msk                  (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  INSx  ========================================================== */
#define DSP_INS_INS1_Pos                  (16UL)                    /*!< INS1 (Bit 16)                                         */
#define DSP_INS_INS1_Msk                  (0xffff0000UL)            /*!< INS1 (Bitfield-Mask: 0xffff)                          */
#define DSP_INS_INS0_Pos                  (0UL)                     /*!< INS0 (Bit 0)                                          */
#define DSP_INS_INS0_Msk                  (0xffffUL)                /*!< INS0 (Bitfield-Mask: 0xffff)                          */


/* =========================================================================================================================== */
/* ================                                           LPTIM                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define LPTIM_CR_WK_IE_Pos                (8UL)                     /*!< WK_IE (Bit 8)                                         */
#define LPTIM_CR_WK_IE_Msk                (0x100UL)                 /*!< WK_IE (Bitfield-Mask: 0x01)                           */
#define LPTIM_CR_WK_EN_Pos                (0UL)                     /*!< WK_EN (Bit 0)                                         */
#define LPTIM_CR_WK_EN_Msk                (0x1UL)                   /*!< WK_EN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SR  =========================================================== */
#define LPTIM_SR_WK_IF_Pos                (0UL)                     /*!< WK_IF (Bit 0)                                         */
#define LPTIM_SR_WK_IF_Msk                (0x1UL)                   /*!< WK_IF (Bitfield-Mask: 0x01)                           */
/* =======================================================  WAKEUP_CR  ======================================================= */
#define LPTIM_WAKEUP_CR_CNT_Pos           (0UL)                     /*!< CNT (Bit 0)                                           */
#define LPTIM_WAKEUP_CR_CNT_Msk           (0xffffffffUL)            /*!< CNT (Bitfield-Mask: 0xffffffff)                       */
/* =====================================================  WAKEUP_PERIOD  ===================================================== */
#define LPTIM_WAKEUP_PERIOD_WK_P_Pos      (0UL)                     /*!< WK_P (Bit 0)                                          */
#define LPTIM_WAKEUP_PERIOD_WK_P_Msk      (0xffffffffUL)            /*!< WK_P (Bitfield-Mask: 0xffffffff)                      */


/* =========================================================================================================================== */
/* ================                                           SPI                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define SPI_CR_NSS_SEL_Pos                (21UL)                    /*!< NSS_SEL (Bit 21)                                      */
#define SPI_CR_NSS_SEL_Msk                (0x200000UL)              /*!< NSS_SEL (Bitfield-Mask: 0x01)                         */
#define SPI_CR_LSB_FIRST_Pos              (20UL)                    /*!< LSB_FIRST (Bit 20)                                    */
#define SPI_CR_LSB_FIRST_Msk              (0x100000UL)              /*!< LSB_FIRST (Bitfield-Mask: 0x01)                       */
#define SPI_CR_UDRR_IE_Pos                (19UL)                    /*!< UDRR_IE (Bit 19)                                      */
#define SPI_CR_UDRR_IE_Msk                (0x80000UL)               /*!< UDRR_IE (Bitfield-Mask: 0x01)                         */
#define SPI_CR_ERR_IE_Pos                 (18UL)                    /*!< ERR_IE (Bit 18)                                       */
#define SPI_CR_ERR_IE_Msk                 (0x40000UL)               /*!< ERR_IE (Bitfield-Mask: 0x01)                          */
#define SPI_CR_TXE_IE_Pos                 (17UL)                    /*!< TXE_IE (Bit 17)                                       */
#define SPI_CR_TXE_IE_Msk                 (0x20000UL)               /*!< TXE_IE (Bitfield-Mask: 0x01)                          */
#define SPI_CR_RXNE_IE_Pos                (16UL)                    /*!< RXNE_IE (Bit 16)                                      */
#define SPI_CR_RXNE_IE_Msk                (0x10000UL)               /*!< RXNE_IE (Bitfield-Mask: 0x01)                         */
#define SPI_CR_DATA_SIZE_Pos              (8UL)                     /*!< DATA_SIZE (Bit 8)                                     */
#define SPI_CR_DATA_SIZE_Msk              (0xf00UL)                 /*!< DATA_SIZE (Bitfield-Mask: 0x0f)                       */
#define SPI_CR_TX_DMAEN_Pos               (7UL)                     /*!< TX_DMAEN (Bit 7)                                      */
#define SPI_CR_TX_DMAEN_Msk               (0x80UL)                  /*!< TX_DMAEN (Bitfield-Mask: 0x01)                        */
#define SPI_CR_RX_DMAEN_Pos               (6UL)                     /*!< RX_DMAEN (Bit 6)                                      */
#define SPI_CR_RX_DMAEN_Msk               (0x40UL)                  /*!< RX_DMAEN (Bitfield-Mask: 0x01)                        */
#define SPI_CR_TX_EN_Pos                  (5UL)                     /*!< TX_EN (Bit 5)                                         */
#define SPI_CR_TX_EN_Msk                  (0x20UL)                  /*!< TX_EN (Bitfield-Mask: 0x01)                           */
#define SPI_CR_RX_EN_Pos                  (4UL)                     /*!< RX_EN (Bit 4)                                         */
#define SPI_CR_RX_EN_Msk                  (0x10UL)                  /*!< RX_EN (Bitfield-Mask: 0x01)                           */
#define SPI_CR_CPOL_Pos                   (3UL)                     /*!< CPOL (Bit 3)                                          */
#define SPI_CR_CPOL_Msk                   (0x8UL)                   /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define SPI_CR_CPHA_Pos                   (2UL)                     /*!< CPHA (Bit 2)                                          */
#define SPI_CR_CPHA_Msk                   (0x4UL)                   /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define SPI_CR_MASTER_Pos                 (1UL)                     /*!< MASTER (Bit 1)                                        */
#define SPI_CR_MASTER_Msk                 (0x2UL)                   /*!< MASTER (Bitfield-Mask: 0x01)                          */
#define SPI_CR_EN_Pos                     (0UL)                     /*!< EN (Bit 0)                                            */
#define SPI_CR_EN_Msk                     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ISR  ========================================================== */
#define SPI_ISR_BUSY_Pos                  (5UL)                     /*!< BUSY (Bit 5)                                          */
#define SPI_ISR_BUSY_Msk                  (0x20UL)                  /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define SPI_ISR_UDRR_Pos                  (4UL)                     /*!< UDRR (Bit 4)                                          */
#define SPI_ISR_UDRR_Msk                  (0x10UL)                  /*!< UDRR (Bitfield-Mask: 0x01)                            */
#define SPI_ISR_FAULT_ERR_Pos             (3UL)                     /*!< FAULT_ERR (Bit 3)                                     */
#define SPI_ISR_FAULT_ERR_Msk             (0x8UL)                   /*!< FAULT_ERR (Bitfield-Mask: 0x01)                       */
#define SPI_ISR_OVRR_ERR_Pos              (2UL)                     /*!< OVRR_ERR (Bit 2)                                      */
#define SPI_ISR_OVRR_ERR_Msk              (0x4UL)                   /*!< OVRR_ERR (Bitfield-Mask: 0x01)                        */
#define SPI_ISR_TXE_Pos                   (1UL)                     /*!< TXE (Bit 1)                                           */
#define SPI_ISR_TXE_Msk                   (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
#define SPI_ISR_RXNE_Pos                  (0UL)                     /*!< RXNE (Bit 0)                                          */
#define SPI_ISR_RXNE_Msk                  (0x1UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
/* ==========================================================  BRR  ========================================================== */
#define SPI_BRR_BRR_Pos                   (0UL)                     /*!< BRR (Bit 0)                                           */
#define SPI_BRR_BRR_Msk                   (0xffUL)                  /*!< BRR (Bitfield-Mask: 0xff)                             */
/* ==========================================================  TDR  ========================================================== */
#define SPI_TDR_TDR_Pos                   (0UL)                     /*!< TDR (Bit 0)                                           */
#define SPI_TDR_TDR_Msk                   (0xffffUL)                /*!< TDR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  RDR  ========================================================== */
#define SPI_RDR_RDR_Pos                   (0UL)                     /*!< RDR (Bit 0)                                           */
#define SPI_RDR_RDR_Msk                   (0xffffUL)                /*!< RDR (Bitfield-Mask: 0xffff)                           */


/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define CRC_CR_XOR_OUT_Pos                (5UL)                     /*!< XOR_OUT (Bit 5)                                       */
#define CRC_CR_XOR_OUT_Msk                (0x20UL)                  /*!< XOR_OUT (Bitfield-Mask: 0x01)                         */
#define CRC_CR_REV_OUT_Pos                (4UL)                     /*!< REV_OUT (Bit 4)                                       */
#define CRC_CR_REV_OUT_Msk                (0x10UL)                  /*!< REV_OUT (Bitfield-Mask: 0x01)                         */
#define CRC_CR_REV_IN_Pos                 (2UL)                     /*!< REV_IN (Bit 2)                                        */
#define CRC_CR_REV_IN_Msk                 (0xcUL)                   /*!< REV_IN (Bitfield-Mask: 0x03)                          */
#define CRC_CR_MODE_Pos                   (0UL)                     /*!< MODE (Bit 0)                                          */
#define CRC_CR_MODE_Msk                   (0x3UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
/* =========================================================  DATA  ========================================================== */
#define CRC_DATA_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define CRC_DATA_DATA_Msk                 (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  INIT  ========================================================== */
#define CRC_INIT_INIT_Pos                 (0UL)                     /*!< INIT (Bit 0)                                          */
#define CRC_INIT_INIT_Msk                 (0xffffffffUL)            /*!< INIT (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  RESULT  ========================================================= */
#define CRC_RESULT_RESULT_Pos             (0UL)                     /*!< RESULT (Bit 0)                                        */
#define CRC_RESULT_RESULT_Msk             (0xffffffffUL)            /*!< RESULT (Bitfield-Mask: 0xffffffff)                    */


/* =========================================================================================================================== */
/* ================                                            DAC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define DAC_CR_VREF_SEL_Pos               (1UL)                     /*!< VREF_SEL (Bit 1)                                      */
#define DAC_CR_VREF_SEL_Msk               (0x2UL)                   /*!< VREF_SEL (Bitfield-Mask: 0x01)                        */
#define DAC_CR_EN_Pos                     (0UL)                     /*!< EN (Bit 0)                                            */
#define DAC_CR_EN_Msk                     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  DR  =========================================================== */
#define DAC_DR_DATA_Pos                   (0UL)                     /*!< DATA (Bit 0)                                          */
#define DAC_DR_DATA_Msk                   (0xfffUL)                 /*!< DATA (Bitfield-Mask: 0xfff)                           */


/* =========================================================================================================================== */
/* ================                                          ADC_COM                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define ADC_COM_CR_SYNC_TRIG_Pos          (26UL)                    /*!< SYNC_TRIG (Bit 26)                                    */
#define ADC_COM_CR_SYNC_TRIG_Msk          (0x4000000UL)             /*!< SYNC_TRIG (Bitfield-Mask: 0x01)                       */
#define ADC_COM_CR_SPEED_Pos              (25UL)                    /*!< SPEED (Bit 25)                                        */
#define ADC_COM_CR_SPEED_Msk              (0x2000000UL)             /*!< SPEED (Bitfield-Mask: 0x01)                           */
#define ADC_COM_CR_VREF_SEL_Pos           (24UL)                    /*!< VREF_SEL (Bit 24)                                     */
#define ADC_COM_CR_VREF_SEL_Msk           (0x1000000UL)             /*!< VREF_SEL (Bitfield-Mask: 0x01)                        */
#define ADC_COM_CR_PRESC_Pos              (20UL)                    /*!< PRESC (Bit 20)                                        */
#define ADC_COM_CR_PRESC_Msk              (0x700000UL)              /*!< PRESC (Bitfield-Mask: 0x07)                           */
#define ADC_COM_CR_PGA_SEL3_Pos           (19UL)                    /*!< PGA_SEL3 (Bit 19)                                     */
#define ADC_COM_CR_PGA_SEL3_Msk           (0x80000UL)               /*!< PGA_SEL3 (Bitfield-Mask: 0x01)                        */
#define ADC_COM_CR_PGA_SEL2_Pos           (18UL)                    /*!< PGA_SEL2 (Bit 18)                                     */
#define ADC_COM_CR_PGA_SEL2_Msk           (0x40000UL)               /*!< PGA_SEL2 (Bitfield-Mask: 0x01)                        */
#define ADC_COM_CR_PGA_SEL1_Pos           (17UL)                    /*!< PGA_SEL1 (Bit 17)                                     */
#define ADC_COM_CR_PGA_SEL1_Msk           (0x20000UL)               /*!< PGA_SEL1 (Bitfield-Mask: 0x01)                        */
#define ADC_COM_CR_PGA_SEL0_Pos           (16UL)                    /*!< PGA_SEL0 (Bit 16)                                     */
#define ADC_COM_CR_PGA_SEL0_Msk           (0x10000UL)               /*!< PGA_SEL0 (Bitfield-Mask: 0x01)                        */
#define ADC_COM_CR_BUFEN15_Pos            (15UL)                    /*!< BUFEN15 (Bit 15)                                      */
#define ADC_COM_CR_BUFEN15_Msk            (0x8000UL)                /*!< BUFEN15 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_CR_BUFEN14_Pos            (14UL)                    /*!< BUFEN14 (Bit 14)                                      */
#define ADC_COM_CR_BUFEN14_Msk            (0x4000UL)                /*!< BUFEN14 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_CR_BUFEN13_Pos            (13UL)                    /*!< BUFEN13 (Bit 13)                                      */
#define ADC_COM_CR_BUFEN13_Msk            (0x2000UL)                /*!< BUFEN13 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_CR_BUFEN12_Pos            (12UL)                    /*!< BUFEN12 (Bit 12)                                      */
#define ADC_COM_CR_BUFEN12_Msk            (0x1000UL)                /*!< BUFEN12 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_CR_BUFEN11_Pos            (11UL)                    /*!< BUFEN11 (Bit 11)                                      */
#define ADC_COM_CR_BUFEN11_Msk            (0x800UL)                 /*!< BUFEN11 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_CR_BUFEN10_Pos            (10UL)                    /*!< BUFEN10 (Bit 10)                                      */
#define ADC_COM_CR_BUFEN10_Msk            (0x400UL)                 /*!< BUFEN10 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_CR_BUFEN9_Pos             (9UL)                     /*!< BUFEN9 (Bit 9)                                        */
#define ADC_COM_CR_BUFEN9_Msk             (0x200UL)                 /*!< BUFEN9 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_CR_BUFEN8_Pos             (8UL)                     /*!< BUFEN8 (Bit 8)                                        */
#define ADC_COM_CR_BUFEN8_Msk             (0x100UL)                 /*!< BUFEN8 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_CR_BUFEN7_Pos             (7UL)                     /*!< BUFEN7 (Bit 7)                                        */
#define ADC_COM_CR_BUFEN7_Msk             (0x80UL)                  /*!< BUFEN7 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_CR_BUFEN6_Pos             (6UL)                     /*!< BUFEN6 (Bit 6)                                        */
#define ADC_COM_CR_BUFEN6_Msk             (0x40UL)                  /*!< BUFEN6 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_CR_BUFEN5_Pos             (5UL)                     /*!< BUFEN5 (Bit 5)                                        */
#define ADC_COM_CR_BUFEN5_Msk             (0x20UL)                  /*!< BUFEN5 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_CR_BUFEN4_Pos             (4UL)                     /*!< BUFEN4 (Bit 4)                                        */
#define ADC_COM_CR_BUFEN4_Msk             (0x10UL)                  /*!< BUFEN4 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_CR_BUFEN3_Pos             (3UL)                     /*!< BUFEN3 (Bit 3)                                        */
#define ADC_COM_CR_BUFEN3_Msk             (0x8UL)                   /*!< BUFEN3 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_CR_BUFEN2_Pos             (2UL)                     /*!< BUFEN2 (Bit 2)                                        */
#define ADC_COM_CR_BUFEN2_Msk             (0x4UL)                   /*!< BUFEN2 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_CR_BUFEN1_Pos             (1UL)                     /*!< BUFEN1 (Bit 1)                                        */
#define ADC_COM_CR_BUFEN1_Msk             (0x2UL)                   /*!< BUFEN1 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_CR_BUFEN0_Pos             (0UL)                     /*!< BUFEN0 (Bit 0)                                        */
#define ADC_COM_CR_BUFEN0_Msk             (0x1UL)                   /*!< BUFEN0 (Bitfield-Mask: 0x01)                          */
/* =========================================================  SMPT  ========================================================== */
#define ADC_COM_SMPT_SMPT1_Pos            (28UL)                    /*!< SMPT1 (Bit 28)                                        */
#define ADC_COM_SMPT_SMPT1_Msk            (0x70000000UL)            /*!< SMPT1 (Bitfield-Mask: 0x07)                           */
#define ADC_COM_SMPT_SMPT0_Pos            (24UL)                    /*!< SMPT0 (Bit 24)                                        */
#define ADC_COM_SMPT_SMPT0_Msk            (0x7000000UL)             /*!< SMPT0 (Bitfield-Mask: 0x07)                           */
#define ADC_COM_SMPT_SMPT_SEL15_Pos       (15UL)                    /*!< SMPT_SEL15 (Bit 15)                                   */
#define ADC_COM_SMPT_SMPT_SEL15_Msk       (0x8000UL)                /*!< SMPT_SEL15 (Bitfield-Mask: 0x01)                      */
#define ADC_COM_SMPT_SMPT_SEL14_Pos       (14UL)                    /*!< SMPT_SEL14 (Bit 14)                                   */
#define ADC_COM_SMPT_SMPT_SEL14_Msk       (0x4000UL)                /*!< SMPT_SEL14 (Bitfield-Mask: 0x01)                      */
#define ADC_COM_SMPT_SMPT_SEL13_Pos       (13UL)                    /*!< SMPT_SEL13 (Bit 13)                                   */
#define ADC_COM_SMPT_SMPT_SEL13_Msk       (0x2000UL)                /*!< SMPT_SEL13 (Bitfield-Mask: 0x01)                      */
#define ADC_COM_SMPT_SMPT_SEL12_Pos       (12UL)                    /*!< SMPT_SEL12 (Bit 12)                                   */
#define ADC_COM_SMPT_SMPT_SEL12_Msk       (0x1000UL)                /*!< SMPT_SEL12 (Bitfield-Mask: 0x01)                      */
#define ADC_COM_SMPT_SMPT_SEL11_Pos       (11UL)                    /*!< SMPT_SEL11 (Bit 11)                                   */
#define ADC_COM_SMPT_SMPT_SEL11_Msk       (0x800UL)                 /*!< SMPT_SEL11 (Bitfield-Mask: 0x01)                      */
#define ADC_COM_SMPT_SMPT_SEL10_Pos       (10UL)                    /*!< SMPT_SEL10 (Bit 10)                                   */
#define ADC_COM_SMPT_SMPT_SEL10_Msk       (0x400UL)                 /*!< SMPT_SEL10 (Bitfield-Mask: 0x01)                      */
#define ADC_COM_SMPT_SMPT_SEL9_Pos        (9UL)                     /*!< SMPT_SEL9 (Bit 9)                                     */
#define ADC_COM_SMPT_SMPT_SEL9_Msk        (0x200UL)                 /*!< SMPT_SEL9 (Bitfield-Mask: 0x01)                       */
#define ADC_COM_SMPT_SMPT_SEL8_Pos        (8UL)                     /*!< SMPT_SEL8 (Bit 8)                                     */
#define ADC_COM_SMPT_SMPT_SEL8_Msk        (0x100UL)                 /*!< SMPT_SEL8 (Bitfield-Mask: 0x01)                       */
#define ADC_COM_SMPT_SMPT_SEL7_Pos        (7UL)                     /*!< SMPT_SEL7 (Bit 7)                                     */
#define ADC_COM_SMPT_SMPT_SEL7_Msk        (0x80UL)                  /*!< SMPT_SEL7 (Bitfield-Mask: 0x01)                       */
#define ADC_COM_SMPT_SMPT_SEL6_Pos        (6UL)                     /*!< SMPT_SEL6 (Bit 6)                                     */
#define ADC_COM_SMPT_SMPT_SEL6_Msk        (0x40UL)                  /*!< SMPT_SEL6 (Bitfield-Mask: 0x01)                       */
#define ADC_COM_SMPT_SMPT_SEL5_Pos        (5UL)                     /*!< SMPT_SEL5 (Bit 5)                                     */
#define ADC_COM_SMPT_SMPT_SEL5_Msk        (0x20UL)                  /*!< SMPT_SEL5 (Bitfield-Mask: 0x01)                       */
#define ADC_COM_SMPT_SMPT_SEL4_Pos        (4UL)                     /*!< SMPT_SEL4 (Bit 4)                                     */
#define ADC_COM_SMPT_SMPT_SEL4_Msk        (0x10UL)                  /*!< SMPT_SEL4 (Bitfield-Mask: 0x01)                       */
#define ADC_COM_SMPT_SMPT_SEL3_Pos        (3UL)                     /*!< SMPT_SEL3 (Bit 3)                                     */
#define ADC_COM_SMPT_SMPT_SEL3_Msk        (0x8UL)                   /*!< SMPT_SEL3 (Bitfield-Mask: 0x01)                       */
#define ADC_COM_SMPT_SMPT_SEL2_Pos        (2UL)                     /*!< SMPT_SEL2 (Bit 2)                                     */
#define ADC_COM_SMPT_SMPT_SEL2_Msk        (0x4UL)                   /*!< SMPT_SEL2 (Bitfield-Mask: 0x01)                       */
#define ADC_COM_SMPT_SMPT_SEL1_Pos        (1UL)                     /*!< SMPT_SEL1 (Bit 1)                                     */
#define ADC_COM_SMPT_SMPT_SEL1_Msk        (0x2UL)                   /*!< SMPT_SEL1 (Bitfield-Mask: 0x01)                       */
#define ADC_COM_SMPT_SMPT_SEL0_Pos        (0UL)                     /*!< SMPT_SEL0 (Bit 0)                                     */
#define ADC_COM_SMPT_SMPT_SEL0_Msk        (0x1UL)                   /*!< SMPT_SEL0 (Bitfield-Mask: 0x01)                       */
/* =========================================================  SMPC  ========================================================== */
#define ADC_COM_SMPC_OVS_RATE_Pos         (29UL)                    /*!< OVS_RATE (Bit 29)                                     */
#define ADC_COM_SMPC_OVS_RATE_Msk         (0x60000000UL)            /*!< OVS_RATE (Bitfield-Mask: 0x03)                        */
#define ADC_COM_SMPC_OVS_RES_Pos          (26UL)                    /*!< OVS_RES (Bit 26)                                      */
#define ADC_COM_SMPC_OVS_RES_Msk          (0x1c000000UL)            /*!< OVS_RES (Bitfield-Mask: 0x07)                         */
#define ADC_COM_SMPC_NORM_RES_Pos         (24UL)                    /*!< NORM_RES (Bit 24)                                     */
#define ADC_COM_SMPC_NORM_RES_Msk         (0x3000000UL)             /*!< NORM_RES (Bitfield-Mask: 0x03)                        */
#define ADC_COM_SMPC_OVSEN15_Pos          (15UL)                    /*!< OVSEN15 (Bit 15)                                      */
#define ADC_COM_SMPC_OVSEN15_Msk          (0x8000UL)                /*!< OVSEN15 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_SMPC_OVSEN14_Pos          (14UL)                    /*!< OVSEN14 (Bit 14)                                      */
#define ADC_COM_SMPC_OVSEN14_Msk          (0x4000UL)                /*!< OVSEN14 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_SMPC_OVSEN13_Pos          (13UL)                    /*!< OVSEN13 (Bit 13)                                      */
#define ADC_COM_SMPC_OVSEN13_Msk          (0x2000UL)                /*!< OVSEN13 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_SMPC_OVSEN12_Pos          (12UL)                    /*!< OVSEN12 (Bit 12)                                      */
#define ADC_COM_SMPC_OVSEN12_Msk          (0x1000UL)                /*!< OVSEN12 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_SMPC_OVSEN11_Pos          (11UL)                    /*!< OVSEN11 (Bit 11)                                      */
#define ADC_COM_SMPC_OVSEN11_Msk          (0x800UL)                 /*!< OVSEN11 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_SMPC_OVSEN10_Pos          (10UL)                    /*!< OVSEN10 (Bit 10)                                      */
#define ADC_COM_SMPC_OVSEN10_Msk          (0x400UL)                 /*!< OVSEN10 (Bitfield-Mask: 0x01)                         */
#define ADC_COM_SMPC_OVSEN9_Pos           (9UL)                     /*!< OVSEN9 (Bit 9)                                        */
#define ADC_COM_SMPC_OVSEN9_Msk           (0x200UL)                 /*!< OVSEN9 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_SMPC_OVSEN8_Pos           (8UL)                     /*!< OVSEN8 (Bit 8)                                        */
#define ADC_COM_SMPC_OVSEN8_Msk           (0x100UL)                 /*!< OVSEN8 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_SMPC_OVSEN7_Pos           (7UL)                     /*!< OVSEN7 (Bit 7)                                        */
#define ADC_COM_SMPC_OVSEN7_Msk           (0x80UL)                  /*!< OVSEN7 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_SMPC_OVSEN6_Pos           (6UL)                     /*!< OVSEN6 (Bit 6)                                        */
#define ADC_COM_SMPC_OVSEN6_Msk           (0x40UL)                  /*!< OVSEN6 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_SMPC_OVSEN5_Pos           (5UL)                     /*!< OVSEN5 (Bit 5)                                        */
#define ADC_COM_SMPC_OVSEN5_Msk           (0x20UL)                  /*!< OVSEN5 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_SMPC_OVSEN4_Pos           (4UL)                     /*!< OVSEN4 (Bit 4)                                        */
#define ADC_COM_SMPC_OVSEN4_Msk           (0x10UL)                  /*!< OVSEN4 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_SMPC_OVSEN3_Pos           (3UL)                     /*!< OVSEN3 (Bit 3)                                        */
#define ADC_COM_SMPC_OVSEN3_Msk           (0x8UL)                   /*!< OVSEN3 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_SMPC_OVSEN2_Pos           (2UL)                     /*!< OVSEN2 (Bit 2)                                        */
#define ADC_COM_SMPC_OVSEN2_Msk           (0x4UL)                   /*!< OVSEN2 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_SMPC_OVSEN1_Pos           (1UL)                     /*!< OVSEN1 (Bit 1)                                        */
#define ADC_COM_SMPC_OVSEN1_Msk           (0x2UL)                   /*!< OVSEN1 (Bitfield-Mask: 0x01)                          */
#define ADC_COM_SMPC_OVSEN0_Pos           (0UL)                     /*!< OVSEN0 (Bit 0)                                        */
#define ADC_COM_SMPC_OVSEN0_Msk           (0x1UL)                   /*!< OVSEN0 (Bitfield-Mask: 0x01)                          */
/* ======================================================  CH_OFFSETx  ======================================================= */
#define ADC_COM_CH_OFFSET_VALUE_Pos       (0UL)                     /*!< VALUE (Bit 0)                                         */
#define ADC_COM_CH_OFFSET_VALUE_Msk       (0xfffUL)                 /*!< VALUE (Bitfield-Mask: 0xfff)                          */


/* =========================================================================================================================== */
/* ================                                           ADC                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  ISR  ========================================================== */
#define ADC_ISR_AWD_CH15_Pos              (31UL)                    /*!< AWD_CH15 (Bit 31)                                     */
#define ADC_ISR_AWD_CH15_Msk              (0x80000000UL)            /*!< AWD_CH15 (Bitfield-Mask: 0x01)                        */
#define ADC_ISR_AWD_CH14_Pos              (30UL)                    /*!< AWD_CH14 (Bit 30)                                     */
#define ADC_ISR_AWD_CH14_Msk              (0x40000000UL)            /*!< AWD_CH14 (Bitfield-Mask: 0x01)                        */
#define ADC_ISR_AWD_CH13_Pos              (29UL)                    /*!< AWD_CH13 (Bit 29)                                     */
#define ADC_ISR_AWD_CH13_Msk              (0x20000000UL)            /*!< AWD_CH13 (Bitfield-Mask: 0x01)                        */
#define ADC_ISR_AWD_CH12_Pos              (28UL)                    /*!< AWD_CH12 (Bit 28)                                     */
#define ADC_ISR_AWD_CH12_Msk              (0x10000000UL)            /*!< AWD_CH12 (Bitfield-Mask: 0x01)                        */
#define ADC_ISR_AWD_CH11_Pos              (27UL)                    /*!< AWD_CH11 (Bit 27)                                     */
#define ADC_ISR_AWD_CH11_Msk              (0x8000000UL)             /*!< AWD_CH11 (Bitfield-Mask: 0x01)                        */
#define ADC_ISR_AWD_CH10_Pos              (26UL)                    /*!< AWD_CH10 (Bit 26)                                     */
#define ADC_ISR_AWD_CH10_Msk              (0x4000000UL)             /*!< AWD_CH10 (Bitfield-Mask: 0x01)                        */
#define ADC_ISR_AWD_CH9_Pos               (25UL)                    /*!< AWD_CH9 (Bit 25)                                      */
#define ADC_ISR_AWD_CH9_Msk               (0x2000000UL)             /*!< AWD_CH9 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_AWD_CH8_Pos               (24UL)                    /*!< AWD_CH8 (Bit 24)                                      */
#define ADC_ISR_AWD_CH8_Msk               (0x1000000UL)             /*!< AWD_CH8 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_AWD_CH7_Pos               (23UL)                    /*!< AWD_CH7 (Bit 23)                                      */
#define ADC_ISR_AWD_CH7_Msk               (0x800000UL)              /*!< AWD_CH7 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_AWD_CH6_Pos               (22UL)                    /*!< AWD_CH6 (Bit 22)                                      */
#define ADC_ISR_AWD_CH6_Msk               (0x400000UL)              /*!< AWD_CH6 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_AWD_CH5_Pos               (21UL)                    /*!< AWD_CH5 (Bit 21)                                      */
#define ADC_ISR_AWD_CH5_Msk               (0x200000UL)              /*!< AWD_CH5 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_AWD_CH4_Pos               (20UL)                    /*!< AWD_CH4 (Bit 20)                                      */
#define ADC_ISR_AWD_CH4_Msk               (0x100000UL)              /*!< AWD_CH4 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_AWD_CH3_Pos               (19UL)                    /*!< AWD_CH3 (Bit 19)                                      */
#define ADC_ISR_AWD_CH3_Msk               (0x80000UL)               /*!< AWD_CH3 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_AWD_CH2_Pos               (18UL)                    /*!< AWD_CH2 (Bit 18)                                      */
#define ADC_ISR_AWD_CH2_Msk               (0x40000UL)               /*!< AWD_CH2 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_AWD_CH1_Pos               (17UL)                    /*!< AWD_CH1 (Bit 17)                                      */
#define ADC_ISR_AWD_CH1_Msk               (0x20000UL)               /*!< AWD_CH1 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_AWD_CH0_Pos               (16UL)                    /*!< AWD_CH0 (Bit 16)                                      */
#define ADC_ISR_AWD_CH0_Msk               (0x10000UL)               /*!< AWD_CH0 (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_OVR_EOI_Pos               (14UL)                    /*!< OVR_EOI (Bit 14)                                      */
#define ADC_ISR_OVR_EOI_Msk               (0x4000UL)                /*!< OVR_EOI (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_OVR_EOC_Pos               (13UL)                    /*!< OVR_EOC (Bit 13)                                      */
#define ADC_ISR_OVR_EOC_Msk               (0x2000UL)                /*!< OVR_EOC (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_OVR_EOT1_Pos              (12UL)                    /*!< OVR_EOT1 (Bit 12)                                     */
#define ADC_ISR_OVR_EOT1_Msk              (0x1000UL)                /*!< OVR_EOT1 (Bitfield-Mask: 0x01)                        */
#define ADC_ISR_OVR_EOT0_Pos              (11UL)                    /*!< OVR_EOT0 (Bit 11)                                     */
#define ADC_ISR_OVR_EOT0_Msk              (0x800UL)                 /*!< OVR_EOT0 (Bitfield-Mask: 0x01)                        */
#define ADC_ISR_OVR_EOS_Pos               (10UL)                    /*!< OVR_EOS (Bit 10)                                      */
#define ADC_ISR_OVR_EOS_Msk               (0x400UL)                 /*!< OVR_EOS (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_EOI_Pos                   (8UL)                     /*!< EOI (Bit 8)                                           */
#define ADC_ISR_EOI_Msk                   (0x100UL)                 /*!< EOI (Bitfield-Mask: 0x01)                             */
#define ADC_ISR_EOC_Pos                   (7UL)                     /*!< EOC (Bit 7)                                           */
#define ADC_ISR_EOC_Msk                   (0x80UL)                  /*!< EOC (Bitfield-Mask: 0x01)                             */
#define ADC_ISR_EOT1_Pos                  (6UL)                     /*!< EOT1 (Bit 6)                                          */
#define ADC_ISR_EOT1_Msk                  (0x40UL)                  /*!< EOT1 (Bitfield-Mask: 0x01)                            */
#define ADC_ISR_EOT0_Pos                  (5UL)                     /*!< EOT0 (Bit 5)                                          */
#define ADC_ISR_EOT0_Msk                  (0x20UL)                  /*!< EOT0 (Bitfield-Mask: 0x01)                            */
#define ADC_ISR_EOS_Pos                   (4UL)                     /*!< EOS (Bit 4)                                           */
#define ADC_ISR_EOS_Msk                   (0x10UL)                  /*!< EOS (Bitfield-Mask: 0x01)                             */
#define ADC_ISR_AWD_SUM_Pos               (2UL)                     /*!< AWD_SUM (Bit 2)                                       */
#define ADC_ISR_AWD_SUM_Msk               (0x4UL)                   /*!< AWD_SUM (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_OVR_SUM_Pos               (1UL)                     /*!< OVR_SUM (Bit 1)                                       */
#define ADC_ISR_OVR_SUM_Msk               (0x2UL)                   /*!< OVR_SUM (Bitfield-Mask: 0x01)                         */
#define ADC_ISR_EO_SUM_Pos                (0UL)                     /*!< EO_SUM (Bit 0)                                        */
#define ADC_ISR_EO_SUM_Msk                (0x1UL)                   /*!< EO_SUM (Bitfield-Mask: 0x01)                          */
/* ==========================================================  IE  =========================================================== */
#define ADC_IE_AWD_Pos                    (13UL)                    /*!< AWD (Bit 13)                                          */
#define ADC_IE_AWD_Msk                    (0x2000UL)                /*!< AWD (Bitfield-Mask: 0x01)                             */
#define ADC_IE_OVR_Pos                    (12UL)                    /*!< OVR (Bit 12)                                          */
#define ADC_IE_OVR_Msk                    (0x1000UL)                /*!< OVR (Bitfield-Mask: 0x01)                             */
#define ADC_IE_EOI_Pos                    (8UL)                     /*!< EOI (Bit 8)                                           */
#define ADC_IE_EOI_Msk                    (0x100UL)                 /*!< EOI (Bitfield-Mask: 0x01)                             */
#define ADC_IE_EOC_Pos                    (7UL)                     /*!< EOC (Bit 7)                                           */
#define ADC_IE_EOC_Msk                    (0x80UL)                  /*!< EOC (Bitfield-Mask: 0x01)                             */
#define ADC_IE_EOT1_Pos                   (6UL)                     /*!< EOT1 (Bit 6)                                          */
#define ADC_IE_EOT1_Msk                   (0x40UL)                  /*!< EOT1 (Bitfield-Mask: 0x01)                            */
#define ADC_IE_EOT0_Pos                   (5UL)                     /*!< EOT0 (Bit 5)                                          */
#define ADC_IE_EOT0_Msk                   (0x20UL)                  /*!< EOT0 (Bitfield-Mask: 0x01)                            */
#define ADC_IE_EOS_Pos                    (4UL)                     /*!< EOS (Bit 4)                                           */
#define ADC_IE_EOS_Msk                    (0x10UL)                  /*!< EOS (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CFG  ========================================================== */
#define ADC_CFG_EOT1_DMA_EN_Pos           (4UL)                     /*!< EOT1_DMA_EN (Bit 4)                                   */
#define ADC_CFG_EOT1_DMA_EN_Msk           (0x10UL)                  /*!< EOT1_DMA_EN (Bitfield-Mask: 0x01)                     */
#define ADC_CFG_EOT0_DMA_EN_Pos           (3UL)                     /*!< EOT0_DMA_EN (Bit 3)                                   */
#define ADC_CFG_EOT0_DMA_EN_Msk           (0x8UL)                   /*!< EOT0_DMA_EN (Bitfield-Mask: 0x01)                     */
#define ADC_CFG_EOS_DMA_EN_Pos            (2UL)                     /*!< EOS_DMA_EN (Bit 2)                                    */
#define ADC_CFG_EOS_DMA_EN_Msk            (0x4UL)                   /*!< EOS_DMA_EN (Bitfield-Mask: 0x01)                      */
#define ADC_CFG_EOC_DMA_EN_Pos            (1UL)                     /*!< EOC_DMA_EN (Bit 1)                                    */
#define ADC_CFG_EOC_DMA_EN_Msk            (0x2UL)                   /*!< EOC_DMA_EN (Bitfield-Mask: 0x01)                      */
#define ADC_CFG_ADC_EN_Pos                (0UL)                     /*!< ADC_EN (Bit 0)                                        */
#define ADC_CFG_ADC_EN_Msk                (0x1UL)                   /*!< ADC_EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  FMT_CR  ========================================================= */
#define ADC_FMT_CR_ALIGN15_Pos            (31UL)                    /*!< ALIGN15 (Bit 31)                                      */
#define ADC_FMT_CR_ALIGN15_Msk            (0x80000000UL)            /*!< ALIGN15 (Bitfield-Mask: 0x01)                         */
#define ADC_FMT_CR_ALIGN14_Pos            (30UL)                    /*!< ALIGN14 (Bit 30)                                      */
#define ADC_FMT_CR_ALIGN14_Msk            (0x40000000UL)            /*!< ALIGN14 (Bitfield-Mask: 0x01)                         */
#define ADC_FMT_CR_ALIGN13_Pos            (29UL)                    /*!< ALIGN13 (Bit 29)                                      */
#define ADC_FMT_CR_ALIGN13_Msk            (0x20000000UL)            /*!< ALIGN13 (Bitfield-Mask: 0x01)                         */
#define ADC_FMT_CR_ALIGN12_Pos            (28UL)                    /*!< ALIGN12 (Bit 28)                                      */
#define ADC_FMT_CR_ALIGN12_Msk            (0x10000000UL)            /*!< ALIGN12 (Bitfield-Mask: 0x01)                         */
#define ADC_FMT_CR_ALIGN11_Pos            (27UL)                    /*!< ALIGN11 (Bit 27)                                      */
#define ADC_FMT_CR_ALIGN11_Msk            (0x8000000UL)             /*!< ALIGN11 (Bitfield-Mask: 0x01)                         */
#define ADC_FMT_CR_ALIGN10_Pos            (26UL)                    /*!< ALIGN10 (Bit 26)                                      */
#define ADC_FMT_CR_ALIGN10_Msk            (0x4000000UL)             /*!< ALIGN10 (Bitfield-Mask: 0x01)                         */
#define ADC_FMT_CR_ALIGN9_Pos             (25UL)                    /*!< ALIGN9 (Bit 25)                                       */
#define ADC_FMT_CR_ALIGN9_Msk             (0x2000000UL)             /*!< ALIGN9 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_ALIGN8_Pos             (24UL)                    /*!< ALIGN8 (Bit 24)                                       */
#define ADC_FMT_CR_ALIGN8_Msk             (0x1000000UL)             /*!< ALIGN8 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_ALIGN7_Pos             (23UL)                    /*!< ALIGN7 (Bit 23)                                       */
#define ADC_FMT_CR_ALIGN7_Msk             (0x800000UL)              /*!< ALIGN7 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_ALIGN6_Pos             (22UL)                    /*!< ALIGN6 (Bit 22)                                       */
#define ADC_FMT_CR_ALIGN6_Msk             (0x400000UL)              /*!< ALIGN6 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_ALIGN5_Pos             (21UL)                    /*!< ALIGN5 (Bit 21)                                       */
#define ADC_FMT_CR_ALIGN5_Msk             (0x200000UL)              /*!< ALIGN5 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_ALIGN4_Pos             (20UL)                    /*!< ALIGN4 (Bit 20)                                       */
#define ADC_FMT_CR_ALIGN4_Msk             (0x100000UL)              /*!< ALIGN4 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_ALIGN3_Pos             (19UL)                    /*!< ALIGN3 (Bit 19)                                       */
#define ADC_FMT_CR_ALIGN3_Msk             (0x80000UL)               /*!< ALIGN3 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_ALIGN2_Pos             (18UL)                    /*!< ALIGN2 (Bit 18)                                       */
#define ADC_FMT_CR_ALIGN2_Msk             (0x40000UL)               /*!< ALIGN2 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_ALIGN1_Pos             (17UL)                    /*!< ALIGN1 (Bit 17)                                       */
#define ADC_FMT_CR_ALIGN1_Msk             (0x20000UL)               /*!< ALIGN1 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_ALIGN0_Pos             (16UL)                    /*!< ALIGN0 (Bit 16)                                       */
#define ADC_FMT_CR_ALIGN0_Msk             (0x10000UL)               /*!< ALIGN0 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_SIGN15_Pos             (15UL)                    /*!< SIGN15 (Bit 15)                                       */
#define ADC_FMT_CR_SIGN15_Msk             (0x8000UL)                /*!< SIGN15 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_SIGN14_Pos             (14UL)                    /*!< SIGN14 (Bit 14)                                       */
#define ADC_FMT_CR_SIGN14_Msk             (0x4000UL)                /*!< SIGN14 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_SIGN13_Pos             (13UL)                    /*!< SIGN13 (Bit 13)                                       */
#define ADC_FMT_CR_SIGN13_Msk             (0x2000UL)                /*!< SIGN13 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_SIGN12_Pos             (12UL)                    /*!< SIGN12 (Bit 12)                                       */
#define ADC_FMT_CR_SIGN12_Msk             (0x1000UL)                /*!< SIGN12 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_SIGN11_Pos             (11UL)                    /*!< SIGN11 (Bit 11)                                       */
#define ADC_FMT_CR_SIGN11_Msk             (0x800UL)                 /*!< SIGN11 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_SIGN10_Pos             (10UL)                    /*!< SIGN10 (Bit 10)                                       */
#define ADC_FMT_CR_SIGN10_Msk             (0x400UL)                 /*!< SIGN10 (Bitfield-Mask: 0x01)                          */
#define ADC_FMT_CR_SIGN9_Pos              (9UL)                     /*!< SIGN9 (Bit 9)                                         */
#define ADC_FMT_CR_SIGN9_Msk              (0x200UL)                 /*!< SIGN9 (Bitfield-Mask: 0x01)                           */
#define ADC_FMT_CR_SIGN8_Pos              (8UL)                     /*!< SIGN8 (Bit 8)                                         */
#define ADC_FMT_CR_SIGN8_Msk              (0x100UL)                 /*!< SIGN8 (Bitfield-Mask: 0x01)                           */
#define ADC_FMT_CR_SIGN7_Pos              (7UL)                     /*!< SIGN7 (Bit 7)                                         */
#define ADC_FMT_CR_SIGN7_Msk              (0x80UL)                  /*!< SIGN7 (Bitfield-Mask: 0x01)                           */
#define ADC_FMT_CR_SIGN6_Pos              (6UL)                     /*!< SIGN6 (Bit 6)                                         */
#define ADC_FMT_CR_SIGN6_Msk              (0x40UL)                  /*!< SIGN6 (Bitfield-Mask: 0x01)                           */
#define ADC_FMT_CR_SIGN5_Pos              (5UL)                     /*!< SIGN5 (Bit 5)                                         */
#define ADC_FMT_CR_SIGN5_Msk              (0x20UL)                  /*!< SIGN5 (Bitfield-Mask: 0x01)                           */
#define ADC_FMT_CR_SIGN4_Pos              (4UL)                     /*!< SIGN4 (Bit 4)                                         */
#define ADC_FMT_CR_SIGN4_Msk              (0x10UL)                  /*!< SIGN4 (Bitfield-Mask: 0x01)                           */
#define ADC_FMT_CR_SIGN3_Pos              (3UL)                     /*!< SIGN3 (Bit 3)                                         */
#define ADC_FMT_CR_SIGN3_Msk              (0x8UL)                   /*!< SIGN3 (Bitfield-Mask: 0x01)                           */
#define ADC_FMT_CR_SIGN2_Pos              (2UL)                     /*!< SIGN2 (Bit 2)                                         */
#define ADC_FMT_CR_SIGN2_Msk              (0x4UL)                   /*!< SIGN2 (Bitfield-Mask: 0x01)                           */
#define ADC_FMT_CR_SIGN1_Pos              (1UL)                     /*!< SIGN1 (Bit 1)                                         */
#define ADC_FMT_CR_SIGN1_Msk              (0x2UL)                   /*!< SIGN1 (Bitfield-Mask: 0x01)                           */
#define ADC_FMT_CR_SIGN0_Pos              (0UL)                     /*!< SIGN0 (Bit 0)                                         */
#define ADC_FMT_CR_SIGN0_Msk              (0x1UL)                   /*!< SIGN0 (Bitfield-Mask: 0x01)                           */
/* ========================================================  TRIG_CR  ======================================================== */
#define ADC_TRIG_CR_HW1_CH_Pos            (28UL)                    /*!< HW1_CH (Bit 28)                                       */
#define ADC_TRIG_CR_HW1_CH_Msk            (0xf0000000UL)            /*!< HW1_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_TRIG_CR_HW1_SRC_Pos           (24UL)                    /*!< HW1_SRC (Bit 24)                                      */
#define ADC_TRIG_CR_HW1_SRC_Msk           (0xf000000UL)             /*!< HW1_SRC (Bitfield-Mask: 0x0f)                         */
#define ADC_TRIG_CR_HW0_CH_Pos            (20UL)                    /*!< HW0_CH (Bit 20)                                       */
#define ADC_TRIG_CR_HW0_CH_Msk            (0xf00000UL)              /*!< HW0_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_TRIG_CR_HW0_SRC_Pos           (16UL)                    /*!< HW0_SRC (Bit 16)                                      */
#define ADC_TRIG_CR_HW0_SRC_Msk           (0xf0000UL)               /*!< HW0_SRC (Bitfield-Mask: 0x0f)                         */
#define ADC_TRIG_CR_SW_CH_Pos             (12UL)                    /*!< SW_CH (Bit 12)                                        */
#define ADC_TRIG_CR_SW_CH_Msk             (0xf000UL)                /*!< SW_CH (Bitfield-Mask: 0x0f)                           */
#define ADC_TRIG_CR_CONT_WAIT_Pos         (8UL)                     /*!< CONT_WAIT (Bit 8)                                     */
#define ADC_TRIG_CR_CONT_WAIT_Msk         (0x700UL)                 /*!< CONT_WAIT (Bitfield-Mask: 0x07)                       */
#define ADC_TRIG_CR_STOP_Pos              (7UL)                     /*!< STOP (Bit 7)                                          */
#define ADC_TRIG_CR_STOP_Msk              (0x80UL)                  /*!< STOP (Bitfield-Mask: 0x01)                            */
#define ADC_TRIG_CR_HW1_EN_Pos            (6UL)                     /*!< HW1_EN (Bit 6)                                        */
#define ADC_TRIG_CR_HW1_EN_Msk            (0x40UL)                  /*!< HW1_EN (Bitfield-Mask: 0x01)                          */
#define ADC_TRIG_CR_HW0_EN_Pos            (5UL)                     /*!< HW0_EN (Bit 5)                                        */
#define ADC_TRIG_CR_HW0_EN_Msk            (0x20UL)                  /*!< HW0_EN (Bitfield-Mask: 0x01)                          */
#define ADC_TRIG_CR_SW_START_Pos          (4UL)                     /*!< SW_START (Bit 4)                                      */
#define ADC_TRIG_CR_SW_START_Msk          (0x10UL)                  /*!< SW_START (Bitfield-Mask: 0x01)                        */
#define ADC_TRIG_CR_MODE_Pos              (0UL)                     /*!< MODE (Bit 0)                                          */
#define ADC_TRIG_CR_MODE_Msk              (0x7UL)                   /*!< MODE (Bitfield-Mask: 0x07)                            */
/* ========================================================  INJ_CR  ========================================================= */
#define ADC_INJ_CR_START_Pos              (4UL)                     /*!< START (Bit 4)                                         */
#define ADC_INJ_CR_START_Msk              (0x10UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
#define ADC_INJ_CR_CH_Pos                 (0UL)                     /*!< CH (Bit 0)                                            */
#define ADC_INJ_CR_CH_Msk                 (0xfUL)                   /*!< CH (Bitfield-Mask: 0x0f)                              */
/* ========================================================  AWD_CR  ========================================================= */
#define ADC_AWD_CR_WH_Pos                 (26UL)                    /*!< WH (Bit 26)                                           */
#define ADC_AWD_CR_WH_Msk                 (0x4000000UL)             /*!< WH (Bitfield-Mask: 0x01)                              */
#define ADC_AWD_CR_WM_Pos                 (25UL)                    /*!< WM (Bit 25)                                           */
#define ADC_AWD_CR_WM_Msk                 (0x2000000UL)             /*!< WM (Bitfield-Mask: 0x01)                              */
#define ADC_AWD_CR_WL_Pos                 (24UL)                    /*!< WL (Bit 24)                                           */
#define ADC_AWD_CR_WL_Msk                 (0x1000000UL)             /*!< WL (Bitfield-Mask: 0x01)                              */
#define ADC_AWD_CR_EN15_Pos               (15UL)                    /*!< EN15 (Bit 15)                                         */
#define ADC_AWD_CR_EN15_Msk               (0x8000UL)                /*!< EN15 (Bitfield-Mask: 0x01)                            */
#define ADC_AWD_CR_EN14_Pos               (14UL)                    /*!< EN14 (Bit 14)                                         */
#define ADC_AWD_CR_EN14_Msk               (0x4000UL)                /*!< EN14 (Bitfield-Mask: 0x01)                            */
#define ADC_AWD_CR_EN13_Pos               (13UL)                    /*!< EN13 (Bit 13)                                         */
#define ADC_AWD_CR_EN13_Msk               (0x2000UL)                /*!< EN13 (Bitfield-Mask: 0x01)                            */
#define ADC_AWD_CR_EN12_Pos               (12UL)                    /*!< EN12 (Bit 12)                                         */
#define ADC_AWD_CR_EN12_Msk               (0x1000UL)                /*!< EN12 (Bitfield-Mask: 0x01)                            */
#define ADC_AWD_CR_EN11_Pos               (11UL)                    /*!< EN11 (Bit 11)                                         */
#define ADC_AWD_CR_EN11_Msk               (0x800UL)                 /*!< EN11 (Bitfield-Mask: 0x01)                            */
#define ADC_AWD_CR_EN10_Pos               (10UL)                    /*!< EN10 (Bit 10)                                         */
#define ADC_AWD_CR_EN10_Msk               (0x400UL)                 /*!< EN10 (Bitfield-Mask: 0x01)                            */
#define ADC_AWD_CR_EN9_Pos                (9UL)                     /*!< EN9 (Bit 9)                                           */
#define ADC_AWD_CR_EN9_Msk                (0x200UL)                 /*!< EN9 (Bitfield-Mask: 0x01)                             */
#define ADC_AWD_CR_EN8_Pos                (8UL)                     /*!< EN8 (Bit 8)                                           */
#define ADC_AWD_CR_EN8_Msk                (0x100UL)                 /*!< EN8 (Bitfield-Mask: 0x01)                             */
#define ADC_AWD_CR_EN7_Pos                (7UL)                     /*!< EN7 (Bit 7)                                           */
#define ADC_AWD_CR_EN7_Msk                (0x80UL)                  /*!< EN7 (Bitfield-Mask: 0x01)                             */
#define ADC_AWD_CR_EN6_Pos                (6UL)                     /*!< EN6 (Bit 6)                                           */
#define ADC_AWD_CR_EN6_Msk                (0x40UL)                  /*!< EN6 (Bitfield-Mask: 0x01)                             */
#define ADC_AWD_CR_EN5_Pos                (5UL)                     /*!< EN5 (Bit 5)                                           */
#define ADC_AWD_CR_EN5_Msk                (0x20UL)                  /*!< EN5 (Bitfield-Mask: 0x01)                             */
#define ADC_AWD_CR_EN4_Pos                (4UL)                     /*!< EN4 (Bit 4)                                           */
#define ADC_AWD_CR_EN4_Msk                (0x10UL)                  /*!< EN4 (Bitfield-Mask: 0x01)                             */
#define ADC_AWD_CR_EN3_Pos                (3UL)                     /*!< EN3 (Bit 3)                                           */
#define ADC_AWD_CR_EN3_Msk                (0x8UL)                   /*!< EN3 (Bitfield-Mask: 0x01)                             */
#define ADC_AWD_CR_EN2_Pos                (2UL)                     /*!< EN2 (Bit 2)                                           */
#define ADC_AWD_CR_EN2_Msk                (0x4UL)                   /*!< EN2 (Bitfield-Mask: 0x01)                             */
#define ADC_AWD_CR_EN1_Pos                (1UL)                     /*!< EN1 (Bit 1)                                           */
#define ADC_AWD_CR_EN1_Msk                (0x2UL)                   /*!< EN1 (Bitfield-Mask: 0x01)                             */
#define ADC_AWD_CR_EN0_Pos                (0UL)                     /*!< EN0 (Bit 0)                                           */
#define ADC_AWD_CR_EN0_Msk                (0x1UL)                   /*!< EN0 (Bitfield-Mask: 0x01)                             */
/* ========================================================  AWD_TH  ========================================================= */
#define ADC_AWD_TH_HT_Pos                 (16UL)                    /*!< HT (Bit 16)                                           */
#define ADC_AWD_TH_HT_Msk                 (0xffff0000UL)            /*!< HT (Bitfield-Mask: 0xffff)                            */
#define ADC_AWD_TH_LT_Pos                 (0UL)                     /*!< LT (Bit 0)                                            */
#define ADC_AWD_TH_LT_Msk                 (0xffffUL)                /*!< LT (Bitfield-Mask: 0xffff)                            */
/* =======================================================  SCAN_SQR0  ======================================================= */
#define ADC_SCAN_SQR0_SQ5_CH_Pos          (28UL)                    /*!< SQ5_CH (Bit 28)                                       */
#define ADC_SCAN_SQR0_SQ5_CH_Msk          (0xf0000000UL)            /*!< SQ5_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_SCAN_SQR0_SQ4_CH_Pos          (24UL)                    /*!< SQ4_CH (Bit 24)                                       */
#define ADC_SCAN_SQR0_SQ4_CH_Msk          (0xf000000UL)             /*!< SQ4_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_SCAN_SQR0_SQ3_CH_Pos          (20UL)                    /*!< SQ3_CH (Bit 20)                                       */
#define ADC_SCAN_SQR0_SQ3_CH_Msk          (0xf00000UL)              /*!< SQ3_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_SCAN_SQR0_SQ2_CH_Pos          (16UL)                    /*!< SQ2_CH (Bit 16)                                       */
#define ADC_SCAN_SQR0_SQ2_CH_Msk          (0xf0000UL)               /*!< SQ2_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_SCAN_SQR0_SQ1_CH_Pos          (12UL)                    /*!< SQ1_CH (Bit 12)                                       */
#define ADC_SCAN_SQR0_SQ1_CH_Msk          (0xf000UL)                /*!< SQ1_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_SCAN_SQR0_SQ0_CH_Pos          (8UL)                     /*!< SQ0_CH (Bit 8)                                        */
#define ADC_SCAN_SQR0_SQ0_CH_Msk          (0xf00UL)                 /*!< SQ0_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_SCAN_SQR0_LEN_Pos             (0UL)                     /*!< LEN (Bit 0)                                           */
#define ADC_SCAN_SQR0_LEN_Msk             (0xfUL)                   /*!< LEN (Bitfield-Mask: 0x0f)                             */
/* =======================================================  SCAN_SQR1  ======================================================= */
#define ADC_SCAN_SQR1_SQ13_CH_Pos         (28UL)                    /*!< SQ13_CH (Bit 28)                                      */
#define ADC_SCAN_SQR1_SQ13_CH_Msk         (0xf0000000UL)            /*!< SQ13_CH (Bitfield-Mask: 0x0f)                         */
#define ADC_SCAN_SQR1_SQ12_CH_Pos         (24UL)                    /*!< SQ12_CH (Bit 24)                                      */
#define ADC_SCAN_SQR1_SQ12_CH_Msk         (0xf000000UL)             /*!< SQ12_CH (Bitfield-Mask: 0x0f)                         */
#define ADC_SCAN_SQR1_SQ11_CH_Pos         (20UL)                    /*!< SQ11_CH (Bit 20)                                      */
#define ADC_SCAN_SQR1_SQ11_CH_Msk         (0xf00000UL)              /*!< SQ11_CH (Bitfield-Mask: 0x0f)                         */
#define ADC_SCAN_SQR1_SQ10_CH_Pos         (16UL)                    /*!< SQ10_CH (Bit 16)                                      */
#define ADC_SCAN_SQR1_SQ10_CH_Msk         (0xf0000UL)               /*!< SQ10_CH (Bitfield-Mask: 0x0f)                         */
#define ADC_SCAN_SQR1_SQ9_CH_Pos          (12UL)                    /*!< SQ9_CH (Bit 12)                                       */
#define ADC_SCAN_SQR1_SQ9_CH_Msk          (0xf000UL)                /*!< SQ9_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_SCAN_SQR1_SQ8_CH_Pos          (8UL)                     /*!< SQ8_CH (Bit 8)                                        */
#define ADC_SCAN_SQR1_SQ8_CH_Msk          (0xf00UL)                 /*!< SQ8_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_SCAN_SQR1_SQ7_CH_Pos          (4UL)                     /*!< SQ7_CH (Bit 4)                                        */
#define ADC_SCAN_SQR1_SQ7_CH_Msk          (0xf0UL)                  /*!< SQ7_CH (Bitfield-Mask: 0x0f)                          */
#define ADC_SCAN_SQR1_SQ6_CH_Pos          (0UL)                     /*!< SQ6_CH (Bit 0)                                        */
#define ADC_SCAN_SQR1_SQ6_CH_Msk          (0xfUL)                   /*!< SQ6_CH (Bitfield-Mask: 0x0f)                          */
/* =======================================================  DR_SINGLE  ======================================================= */
#define ADC_DR_SINGLE_DATA_Pos            (0UL)                     /*!< DATA (Bit 0)                                          */
#define ADC_DR_SINGLE_DATA_Msk            (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DR_INJ  ========================================================= */
#define ADC_DR_INJ_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define ADC_DR_INJ_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =======================================================  DR_TRIG0  ======================================================== */
#define ADC_DR_TRIG0_DATA_Pos             (0UL)                     /*!< DATA (Bit 0)                                          */
#define ADC_DR_TRIG0_DATA_Msk             (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =======================================================  DR_TRIG1  ======================================================== */
#define ADC_DR_TRIG1_DATA_Pos             (0UL)                     /*!< DATA (Bit 0)                                          */
#define ADC_DR_TRIG1_DATA_Msk             (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =======================================================  DR_SCANx  ======================================================== */
#define ADC_DR_SCAN_DATA_Pos              (0UL)                     /*!< DATA (Bit 0)                                          */
#define ADC_DR_SCAN_DATA_Msk              (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */


/* =========================================================================================================================== */
/* ================                                            I2C                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define I2C_CR1_PRESC_Pos                 (27UL)                    /*!< PRESC (Bit 27)                                        */
#define I2C_CR1_PRESC_Msk                 (0xf8000000UL)            /*!< PRESC (Bitfield-Mask: 0x1f)                           */
#define I2C_CR1_STARTF_IE_Pos             (25UL)                    /*!< STARTF_IE (Bit 25)                                    */
#define I2C_CR1_STARTF_IE_Msk             (0x2000000UL)             /*!< STARTF_IE (Bitfield-Mask: 0x01)                       */
#define I2C_CR1_ERR_IE_Pos                (24UL)                    /*!< ERR_IE (Bit 24)                                       */
#define I2C_CR1_ERR_IE_Msk                (0x1000000UL)             /*!< ERR_IE (Bitfield-Mask: 0x01)                          */
#define I2C_CR1_RXC_IE_Pos                (23UL)                    /*!< RXC_IE (Bit 23)                                       */
#define I2C_CR1_RXC_IE_Msk                (0x800000UL)              /*!< RXC_IE (Bitfield-Mask: 0x01)                          */
#define I2C_CR1_GC_IE_Pos                 (22UL)                    /*!< GC_IE (Bit 22)                                        */
#define I2C_CR1_GC_IE_Msk                 (0x400000UL)              /*!< GC_IE (Bitfield-Mask: 0x01)                           */
#define I2C_CR1_NACKF_IE_Pos              (21UL)                    /*!< NACKF_IE (Bit 21)                                     */
#define I2C_CR1_NACKF_IE_Msk              (0x200000UL)              /*!< NACKF_IE (Bitfield-Mask: 0x01)                        */
#define I2C_CR1_STOPF_IE_Pos              (20UL)                    /*!< STOPF_IE (Bit 20)                                     */
#define I2C_CR1_STOPF_IE_Msk              (0x100000UL)              /*!< STOPF_IE (Bitfield-Mask: 0x01)                        */
#define I2C_CR1_ADDRM_IE_Pos              (19UL)                    /*!< ADDRM_IE (Bit 19)                                     */
#define I2C_CR1_ADDRM_IE_Msk              (0x80000UL)               /*!< ADDRM_IE (Bitfield-Mask: 0x01)                        */
#define I2C_CR1_RXNE_IE_Pos               (18UL)                    /*!< RXNE_IE (Bit 18)                                      */
#define I2C_CR1_RXNE_IE_Msk               (0x40000UL)               /*!< RXNE_IE (Bitfield-Mask: 0x01)                         */
#define I2C_CR1_TXE_IE_Pos                (17UL)                    /*!< TXE_IE (Bit 17)                                       */
#define I2C_CR1_TXE_IE_Msk                (0x20000UL)               /*!< TXE_IE (Bitfield-Mask: 0x01)                          */
#define I2C_CR1_TXC_IE_Pos                (16UL)                    /*!< TXC_IE (Bit 16)                                       */
#define I2C_CR1_TXC_IE_Msk                (0x10000UL)               /*!< TXC_IE (Bitfield-Mask: 0x01)                          */
#define I2C_CR1_DNF_Pos                   (12UL)                    /*!< DNF (Bit 12)                                          */
#define I2C_CR1_DNF_Msk                   (0xf000UL)                /*!< DNF (Bitfield-Mask: 0x0f)                             */
#define I2C_CR1_TIMEOUT_SEL_Pos           (8UL)                     /*!< TIMEOUT_SEL (Bit 8)                                   */
#define I2C_CR1_TIMEOUT_SEL_Msk           (0x700UL)                 /*!< TIMEOUT_SEL (Bitfield-Mask: 0x07)                     */
#define I2C_CR1_NOADDR_Pos                (7UL)                     /*!< NOADDR (Bit 7)                                        */
#define I2C_CR1_NOADDR_Msk                (0x80UL)                  /*!< NOADDR (Bitfield-Mask: 0x01)                          */
#define I2C_CR1_DIS_SLAVE_Pos             (6UL)                     /*!< DIS_SLAVE (Bit 6)                                     */
#define I2C_CR1_DIS_SLAVE_Msk             (0x40UL)                  /*!< DIS_SLAVE (Bitfield-Mask: 0x01)                       */
#define I2C_CR1_TX_DMAEN_Pos              (5UL)                     /*!< TX_DMAEN (Bit 5)                                      */
#define I2C_CR1_TX_DMAEN_Msk              (0x20UL)                  /*!< TX_DMAEN (Bitfield-Mask: 0x01)                        */
#define I2C_CR1_RX_DMAEN_Pos              (4UL)                     /*!< RX_DMAEN (Bit 4)                                      */
#define I2C_CR1_RX_DMAEN_Msk              (0x10UL)                  /*!< RX_DMAEN (Bitfield-Mask: 0x01)                        */
#define I2C_CR1_GC_EN_Pos                 (3UL)                     /*!< GC_EN (Bit 3)                                         */
#define I2C_CR1_GC_EN_Msk                 (0x8UL)                   /*!< GC_EN (Bitfield-Mask: 0x01)                           */
#define I2C_CR1_NO_STRETCH_Pos            (2UL)                     /*!< NO_STRETCH (Bit 2)                                    */
#define I2C_CR1_NO_STRETCH_Msk            (0x4UL)                   /*!< NO_STRETCH (Bitfield-Mask: 0x01)                      */
#define I2C_CR1_MS_Pos                    (1UL)                     /*!< MS (Bit 1)                                            */
#define I2C_CR1_MS_Msk                    (0x2UL)                   /*!< MS (Bitfield-Mask: 0x01)                              */
#define I2C_CR1_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define I2C_CR1_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR2  ========================================================== */
#define I2C_CR2_RELOAD_Pos                (24UL)                    /*!< RELOAD (Bit 24)                                       */
#define I2C_CR2_RELOAD_Msk                (0x1000000UL)             /*!< RELOAD (Bitfield-Mask: 0x01)                          */
#define I2C_CR2_BYTES_NUM_Pos             (16UL)                    /*!< BYTES_NUM (Bit 16)                                    */
#define I2C_CR2_BYTES_NUM_Msk             (0xff0000UL)              /*!< BYTES_NUM (Bitfield-Mask: 0xff)                       */
#define I2C_CR2_TXE_SET_Pos               (15UL)                    /*!< TXE_SET (Bit 15)                                      */
#define I2C_CR2_TXE_SET_Msk               (0x8000UL)                /*!< TXE_SET (Bitfield-Mask: 0x01)                         */
#define I2C_CR2_NACK_Pos                  (14UL)                    /*!< NACK (Bit 14)                                         */
#define I2C_CR2_NACK_Msk                  (0x4000UL)                /*!< NACK (Bitfield-Mask: 0x01)                            */
#define I2C_CR2_START_STOP_Pos            (12UL)                    /*!< START_STOP (Bit 12)                                   */
#define I2C_CR2_START_STOP_Msk            (0x3000UL)                /*!< START_STOP (Bitfield-Mask: 0x03)                      */
#define I2C_CR2_WR_Pos                    (11UL)                    /*!< WR (Bit 11)                                           */
#define I2C_CR2_WR_Msk                    (0x800UL)                 /*!< WR (Bitfield-Mask: 0x01)                              */
#define I2C_CR2_ADDR10_Pos                (10UL)                    /*!< ADDR10 (Bit 10)                                       */
#define I2C_CR2_ADDR10_Msk                (0x400UL)                 /*!< ADDR10 (Bitfield-Mask: 0x01)                          */
#define I2C_CR2_SADDR_Pos                 (0UL)                     /*!< SADDR (Bit 0)                                         */
#define I2C_CR2_SADDR_Msk                 (0x3ffUL)                 /*!< SADDR (Bitfield-Mask: 0x3ff)                          */
/* ==========================================================  ISR  ========================================================== */
#define I2C_ISR_TIMEOUT_Pos               (15UL)                    /*!< TIMEOUT (Bit 15)                                      */
#define I2C_ISR_TIMEOUT_Msk               (0x8000UL)                /*!< TIMEOUT (Bitfield-Mask: 0x01)                         */
#define I2C_ISR_STARTF_Pos                (14UL)                    /*!< STARTF (Bit 14)                                       */
#define I2C_ISR_STARTF_Msk                (0x4000UL)                /*!< STARTF (Bitfield-Mask: 0x01)                          */
#define I2C_ISR_BUSY_Pos                  (13UL)                    /*!< BUSY (Bit 13)                                         */
#define I2C_ISR_BUSY_Msk                  (0x2000UL)                /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define I2C_ISR_DIR_Pos                   (12UL)                    /*!< DIR (Bit 12)                                          */
#define I2C_ISR_DIR_Msk                   (0x1000UL)                /*!< DIR (Bitfield-Mask: 0x01)                             */
#define I2C_ISR_OVRR_UDRR_Pos             (11UL)                    /*!< OVRR_UDRR (Bit 11)                                    */
#define I2C_ISR_OVRR_UDRR_Msk             (0x800UL)                 /*!< OVRR_UDRR (Bitfield-Mask: 0x01)                       */
#define I2C_ISR_BUS_ERR_Pos               (10UL)                    /*!< BUS_ERR (Bit 10)                                      */
#define I2C_ISR_BUS_ERR_Msk               (0x400UL)                 /*!< BUS_ERR (Bitfield-Mask: 0x01)                         */
#define I2C_ISR_ARBI_LOST_Pos             (9UL)                     /*!< ARBI_LOST (Bit 9)                                     */
#define I2C_ISR_ARBI_LOST_Msk             (0x200UL)                 /*!< ARBI_LOST (Bitfield-Mask: 0x01)                       */
#define I2C_ISR_GC_Pos                    (8UL)                     /*!< GC (Bit 8)                                            */
#define I2C_ISR_GC_Msk                    (0x100UL)                 /*!< GC (Bitfield-Mask: 0x01)                              */
#define I2C_ISR_RXC_Pos                   (7UL)                     /*!< RXC (Bit 7)                                           */
#define I2C_ISR_RXC_Msk                   (0x80UL)                  /*!< RXC (Bitfield-Mask: 0x01)                             */
#define I2C_ISR_RXC_RE_Pos                (6UL)                     /*!< RXC_RE (Bit 6)                                        */
#define I2C_ISR_RXC_RE_Msk                (0x40UL)                  /*!< RXC_RE (Bitfield-Mask: 0x01)                          */
#define I2C_ISR_NACKF_Pos                 (5UL)                     /*!< NACKF (Bit 5)                                         */
#define I2C_ISR_NACKF_Msk                 (0x20UL)                  /*!< NACKF (Bitfield-Mask: 0x01)                           */
#define I2C_ISR_STOPF_Pos                 (4UL)                     /*!< STOPF (Bit 4)                                         */
#define I2C_ISR_STOPF_Msk                 (0x10UL)                  /*!< STOPF (Bitfield-Mask: 0x01)                           */
#define I2C_ISR_ADDRM_Pos                 (3UL)                     /*!< ADDRM (Bit 3)                                         */
#define I2C_ISR_ADDRM_Msk                 (0x8UL)                   /*!< ADDRM (Bitfield-Mask: 0x01)                           */
#define I2C_ISR_RXNE_Pos                  (2UL)                     /*!< RXNE (Bit 2)                                          */
#define I2C_ISR_RXNE_Msk                  (0x4UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define I2C_ISR_TXE_Pos                   (1UL)                     /*!< TXE (Bit 1)                                           */
#define I2C_ISR_TXE_Msk                   (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
#define I2C_ISR_TXC_Pos                   (0UL)                     /*!< TXC (Bit 0)                                           */
#define I2C_ISR_TXC_Msk                   (0x1UL)                   /*!< TXC (Bitfield-Mask: 0x01)                             */
/* ========================================================  TIMING  ========================================================= */
#define I2C_TIMING_SCLDEL_I_Pos           (27UL)                    /*!< SCLDEL_I (Bit 27)                                     */
#define I2C_TIMING_SCLDEL_I_Msk           (0x38000000UL)            /*!< SCLDEL_I (Bitfield-Mask: 0x07)                        */
#define I2C_TIMING_SDADEL_I_Pos           (24UL)                    /*!< SDADEL_I (Bit 24)                                     */
#define I2C_TIMING_SDADEL_I_Msk           (0x7000000UL)             /*!< SDADEL_I (Bitfield-Mask: 0x07)                        */
#define I2C_TIMING_SCLDEL_O_Pos           (20UL)                    /*!< SCLDEL_O (Bit 20)                                     */
#define I2C_TIMING_SCLDEL_O_Msk           (0xf00000UL)              /*!< SCLDEL_O (Bitfield-Mask: 0x0f)                        */
#define I2C_TIMING_SDADEL_O_Pos           (16UL)                    /*!< SDADEL_O (Bit 16)                                     */
#define I2C_TIMING_SDADEL_O_Msk           (0xf0000UL)               /*!< SDADEL_O (Bitfield-Mask: 0x0f)                        */
#define I2C_TIMING_SCLH_Pos               (8UL)                     /*!< SCLH (Bit 8)                                          */
#define I2C_TIMING_SCLH_Msk               (0xff00UL)                /*!< SCLH (Bitfield-Mask: 0xff)                            */
#define I2C_TIMING_SCLL_Pos               (0UL)                     /*!< SCLL (Bit 0)                                          */
#define I2C_TIMING_SCLL_Msk               (0xffUL)                  /*!< SCLL (Bitfield-Mask: 0xff)                            */
/* ==========================================================  OAR  ========================================================== */
#define I2C_OAR_OWN_ADDR10_Pos            (10UL)                    /*!< OWN_ADDR10 (Bit 10)                                   */
#define I2C_OAR_OWN_ADDR10_Msk            (0x400UL)                 /*!< OWN_ADDR10 (Bitfield-Mask: 0x01)                      */
#define I2C_OAR_OWN_ADDR_Pos              (0UL)                     /*!< OWN_ADDR (Bit 0)                                      */
#define I2C_OAR_OWN_ADDR_Msk              (0x3ffUL)                 /*!< OWN_ADDR (Bitfield-Mask: 0x3ff)                       */
/* ==========================================================  TDR  ========================================================== */
#define I2C_TDR_TDR_Pos                   (0UL)                     /*!< TDR (Bit 0)                                           */
#define I2C_TDR_TDR_Msk                   (0xffUL)                  /*!< TDR (Bitfield-Mask: 0xff)                             */
/* ==========================================================  RDR  ========================================================== */
#define I2C_RDR_RDR_Pos                   (0UL)                     /*!< RDR (Bit 0)                                           */
#define I2C_RDR_RDR_Msk                   (0xffUL)                  /*!< RDR (Bitfield-Mask: 0xff)                             */


/* =========================================================================================================================== */
/* ================                                           ACMP                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define ACMP_CR_BEMFR_EN_Pos              (5UL)                     /*!< BEMFR_EN (Bit 5)                                      */
#define ACMP_CR_BEMFR_EN_Msk              (0x20UL)                  /*!< BEMFR_EN (Bitfield-Mask: 0x01)                        */
#define ACMP_CR_VREF_SEL_Pos              (4UL)                     /*!< VREF_SEL (Bit 4)                                      */
#define ACMP_CR_VREF_SEL_Msk              (0x10UL)                  /*!< VREF_SEL (Bitfield-Mask: 0x01)                        */
#define ACMP_CR_RES_SEL_Pos               (0UL)                     /*!< RES_SEL (Bit 0)                                       */
#define ACMP_CR_RES_SEL_Msk               (0xfUL)                   /*!< RES_SEL (Bitfield-Mask: 0x0f)                         */
/* ==========================================================  SR  =========================================================== */
#define ACMP_SR_ACMP3_RDY_Pos             (19UL)                    /*!< ACMP3_RDY (Bit 19)                                    */
#define ACMP_SR_ACMP3_RDY_Msk             (0x80000UL)               /*!< ACMP3_RDY (Bitfield-Mask: 0x01)                       */
#define ACMP_SR_ACMP2_RDY_Pos             (18UL)                    /*!< ACMP2_RDY (Bit 18)                                    */
#define ACMP_SR_ACMP2_RDY_Msk             (0x40000UL)               /*!< ACMP2_RDY (Bitfield-Mask: 0x01)                       */
#define ACMP_SR_ACMP1_RDY_Pos             (17UL)                    /*!< ACMP1_RDY (Bit 17)                                    */
#define ACMP_SR_ACMP1_RDY_Msk             (0x20000UL)               /*!< ACMP1_RDY (Bitfield-Mask: 0x01)                       */
#define ACMP_SR_ACMP0_RDY_Pos             (16UL)                    /*!< ACMP0_RDY (Bit 16)                                    */
#define ACMP_SR_ACMP0_RDY_Msk             (0x10000UL)               /*!< ACMP0_RDY (Bitfield-Mask: 0x01)                       */
#define ACMP_SR_ACMP3_RES_Pos             (11UL)                    /*!< ACMP3_RES (Bit 11)                                    */
#define ACMP_SR_ACMP3_RES_Msk             (0x800UL)                 /*!< ACMP3_RES (Bitfield-Mask: 0x01)                       */
#define ACMP_SR_ACMP2_RES_Pos             (10UL)                    /*!< ACMP2_RES (Bit 10)                                    */
#define ACMP_SR_ACMP2_RES_Msk             (0x400UL)                 /*!< ACMP2_RES (Bitfield-Mask: 0x01)                       */
#define ACMP_SR_ACMP1_RES_Pos             (9UL)                     /*!< ACMP1_RES (Bit 9)                                     */
#define ACMP_SR_ACMP1_RES_Msk             (0x200UL)                 /*!< ACMP1_RES (Bitfield-Mask: 0x01)                       */
#define ACMP_SR_ACMP0_RES_Pos             (8UL)                     /*!< ACMP0_RES (Bit 8)                                     */
#define ACMP_SR_ACMP0_RES_Msk             (0x100UL)                 /*!< ACMP0_RES (Bitfield-Mask: 0x01)                       */
#define ACMP_SR_ACMP3_IF_Pos              (3UL)                     /*!< ACMP3_IF (Bit 3)                                      */
#define ACMP_SR_ACMP3_IF_Msk              (0x8UL)                   /*!< ACMP3_IF (Bitfield-Mask: 0x01)                        */
#define ACMP_SR_ACMP2_IF_Pos              (2UL)                     /*!< ACMP2_IF (Bit 2)                                      */
#define ACMP_SR_ACMP2_IF_Msk              (0x4UL)                   /*!< ACMP2_IF (Bitfield-Mask: 0x01)                        */
#define ACMP_SR_ACMP1_IF_Pos              (1UL)                     /*!< ACMP1_IF (Bit 1)                                      */
#define ACMP_SR_ACMP1_IF_Msk              (0x2UL)                   /*!< ACMP1_IF (Bitfield-Mask: 0x01)                        */
#define ACMP_SR_ACMP0_IF_Pos              (0UL)                     /*!< ACMP0_IF (Bit 0)                                      */
#define ACMP_SR_ACMP0_IF_Msk              (0x1UL)                   /*!< ACMP0_IF (Bitfield-Mask: 0x01)                        */
/* =======================================================  ACMP0_CFG  ======================================================= */
#define ACMP_ACMP0_CFG_IN_N_SEL_Pos       (20UL)                    /*!< IN_N_SEL (Bit 20)                                     */
#define ACMP_ACMP0_CFG_IN_N_SEL_Msk       (0x700000UL)              /*!< IN_N_SEL (Bitfield-Mask: 0x07)                        */
#define ACMP_ACMP0_CFG_IN_P_SEL_Pos       (16UL)                    /*!< IN_P_SEL (Bit 16)                                     */
#define ACMP_ACMP0_CFG_IN_P_SEL_Msk       (0x70000UL)               /*!< IN_P_SEL (Bitfield-Mask: 0x07)                        */
#define ACMP_ACMP0_CFG_FLT_EN_Pos         (12UL)                    /*!< FLT_EN (Bit 12)                                       */
#define ACMP_ACMP0_CFG_FLT_EN_Msk         (0x1000UL)                /*!< FLT_EN (Bitfield-Mask: 0x01)                          */
#define ACMP_ACMP0_CFG_FLT_LEN_Pos        (10UL)                    /*!< FLT_LEN (Bit 10)                                      */
#define ACMP_ACMP0_CFG_FLT_LEN_Msk        (0xc00UL)                 /*!< FLT_LEN (Bitfield-Mask: 0x03)                         */
#define ACMP_ACMP0_CFG_FLT_SAMPLE_Pos     (8UL)                     /*!< FLT_SAMPLE (Bit 8)                                    */
#define ACMP_ACMP0_CFG_FLT_SAMPLE_Msk     (0x300UL)                 /*!< FLT_SAMPLE (Bitfield-Mask: 0x03)                      */
#define ACMP_ACMP0_CFG_HYS_EN_Pos         (6UL)                     /*!< HYS_EN (Bit 6)                                        */
#define ACMP_ACMP0_CFG_HYS_EN_Msk         (0x40UL)                  /*!< HYS_EN (Bitfield-Mask: 0x01)                          */
#define ACMP_ACMP0_CFG_INT_TYPE_Pos       (4UL)                     /*!< INT_TYPE (Bit 4)                                      */
#define ACMP_ACMP0_CFG_INT_TYPE_Msk       (0x30UL)                  /*!< INT_TYPE (Bitfield-Mask: 0x03)                        */
#define ACMP_ACMP0_CFG_IE_Pos             (3UL)                     /*!< IE (Bit 3)                                            */
#define ACMP_ACMP0_CFG_IE_Msk             (0x8UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
#define ACMP_ACMP0_CFG_POL_Pos            (1UL)                     /*!< POL (Bit 1)                                           */
#define ACMP_ACMP0_CFG_POL_Msk            (0x2UL)                   /*!< POL (Bitfield-Mask: 0x01)                             */
#define ACMP_ACMP0_CFG_EN_Pos             (0UL)                     /*!< EN (Bit 0)                                            */
#define ACMP_ACMP0_CFG_EN_Msk             (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  ACMP1_CFG  ======================================================= */
#define ACMP_ACMP1_CFG_IN_N_SEL_Pos       (20UL)                    /*!< IN_N_SEL (Bit 20)                                     */
#define ACMP_ACMP1_CFG_IN_N_SEL_Msk       (0x700000UL)              /*!< IN_N_SEL (Bitfield-Mask: 0x07)                        */
#define ACMP_ACMP1_CFG_IN_P_SEL_Pos       (16UL)                    /*!< IN_P_SEL (Bit 16)                                     */
#define ACMP_ACMP1_CFG_IN_P_SEL_Msk       (0x70000UL)               /*!< IN_P_SEL (Bitfield-Mask: 0x07)                        */
#define ACMP_ACMP1_CFG_FLT_EN_Pos         (12UL)                    /*!< FLT_EN (Bit 12)                                       */
#define ACMP_ACMP1_CFG_FLT_EN_Msk         (0x1000UL)                /*!< FLT_EN (Bitfield-Mask: 0x01)                          */
#define ACMP_ACMP1_CFG_FLT_LEN_Pos        (10UL)                    /*!< FLT_LEN (Bit 10)                                      */
#define ACMP_ACMP1_CFG_FLT_LEN_Msk        (0xc00UL)                 /*!< FLT_LEN (Bitfield-Mask: 0x03)                         */
#define ACMP_ACMP1_CFG_FLT_SAMPLE_Pos     (8UL)                     /*!< FLT_SAMPLE (Bit 8)                                    */
#define ACMP_ACMP1_CFG_FLT_SAMPLE_Msk     (0x300UL)                 /*!< FLT_SAMPLE (Bitfield-Mask: 0x03)                      */
#define ACMP_ACMP1_CFG_HYS_EN_Pos         (6UL)                     /*!< HYS_EN (Bit 6)                                        */
#define ACMP_ACMP1_CFG_HYS_EN_Msk         (0x40UL)                  /*!< HYS_EN (Bitfield-Mask: 0x01)                          */
#define ACMP_ACMP1_CFG_INT_TYPE_Pos       (4UL)                     /*!< INT_TYPE (Bit 4)                                      */
#define ACMP_ACMP1_CFG_INT_TYPE_Msk       (0x30UL)                  /*!< INT_TYPE (Bitfield-Mask: 0x03)                        */
#define ACMP_ACMP1_CFG_IE_Pos             (3UL)                     /*!< IE (Bit 3)                                            */
#define ACMP_ACMP1_CFG_IE_Msk             (0x8UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
#define ACMP_ACMP1_CFG_POL_Pos            (1UL)                     /*!< POL (Bit 1)                                           */
#define ACMP_ACMP1_CFG_POL_Msk            (0x2UL)                   /*!< POL (Bitfield-Mask: 0x01)                             */
#define ACMP_ACMP1_CFG_EN_Pos             (0UL)                     /*!< EN (Bit 0)                                            */
#define ACMP_ACMP1_CFG_EN_Msk             (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  ACMP2_CFG  ======================================================= */
#define ACMP_ACMP2_CFG_IN_N_SEL_Pos       (20UL)                    /*!< IN_N_SEL (Bit 20)                                     */
#define ACMP_ACMP2_CFG_IN_N_SEL_Msk       (0x700000UL)              /*!< IN_N_SEL (Bitfield-Mask: 0x07)                        */
#define ACMP_ACMP2_CFG_IN_P_SEL_Pos       (16UL)                    /*!< IN_P_SEL (Bit 16)                                     */
#define ACMP_ACMP2_CFG_IN_P_SEL_Msk       (0x70000UL)               /*!< IN_P_SEL (Bitfield-Mask: 0x07)                        */
#define ACMP_ACMP2_CFG_FLT_EN_Pos         (12UL)                    /*!< FLT_EN (Bit 12)                                       */
#define ACMP_ACMP2_CFG_FLT_EN_Msk         (0x1000UL)                /*!< FLT_EN (Bitfield-Mask: 0x01)                          */
#define ACMP_ACMP2_CFG_FLT_LEN_Pos        (10UL)                    /*!< FLT_LEN (Bit 10)                                      */
#define ACMP_ACMP2_CFG_FLT_LEN_Msk        (0xc00UL)                 /*!< FLT_LEN (Bitfield-Mask: 0x03)                         */
#define ACMP_ACMP2_CFG_FLT_SAMPLE_Pos     (8UL)                     /*!< FLT_SAMPLE (Bit 8)                                    */
#define ACMP_ACMP2_CFG_FLT_SAMPLE_Msk     (0x300UL)                 /*!< FLT_SAMPLE (Bitfield-Mask: 0x03)                      */
#define ACMP_ACMP2_CFG_HYS_EN_Pos         (6UL)                     /*!< HYS_EN (Bit 6)                                        */
#define ACMP_ACMP2_CFG_HYS_EN_Msk         (0x40UL)                  /*!< HYS_EN (Bitfield-Mask: 0x01)                          */
#define ACMP_ACMP2_CFG_INT_TYPE_Pos       (4UL)                     /*!< INT_TYPE (Bit 4)                                      */
#define ACMP_ACMP2_CFG_INT_TYPE_Msk       (0x30UL)                  /*!< INT_TYPE (Bitfield-Mask: 0x03)                        */
#define ACMP_ACMP2_CFG_IE_Pos             (3UL)                     /*!< IE (Bit 3)                                            */
#define ACMP_ACMP2_CFG_IE_Msk             (0x8UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
#define ACMP_ACMP2_CFG_POL_Pos            (1UL)                     /*!< POL (Bit 1)                                           */
#define ACMP_ACMP2_CFG_POL_Msk            (0x2UL)                   /*!< POL (Bitfield-Mask: 0x01)                             */
#define ACMP_ACMP2_CFG_EN_Pos             (0UL)                     /*!< EN (Bit 0)                                            */
#define ACMP_ACMP2_CFG_EN_Msk             (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  ACMP3_CFG  ======================================================= */
#define ACMP_ACMP3_CFG_IN_N_SEL_Pos       (20UL)                    /*!< IN_N_SEL (Bit 20)                                     */
#define ACMP_ACMP3_CFG_IN_N_SEL_Msk       (0x700000UL)              /*!< IN_N_SEL (Bitfield-Mask: 0x07)                        */
#define ACMP_ACMP3_CFG_IN_P_SEL_Pos       (16UL)                    /*!< IN_P_SEL (Bit 16)                                     */
#define ACMP_ACMP3_CFG_IN_P_SEL_Msk       (0x70000UL)               /*!< IN_P_SEL (Bitfield-Mask: 0x07)                        */
#define ACMP_ACMP3_CFG_FLT_EN_Pos         (12UL)                    /*!< FLT_EN (Bit 12)                                       */
#define ACMP_ACMP3_CFG_FLT_EN_Msk         (0x1000UL)                /*!< FLT_EN (Bitfield-Mask: 0x01)                          */
#define ACMP_ACMP3_CFG_FLT_LEN_Pos        (10UL)                    /*!< FLT_LEN (Bit 10)                                      */
#define ACMP_ACMP3_CFG_FLT_LEN_Msk        (0xc00UL)                 /*!< FLT_LEN (Bitfield-Mask: 0x03)                         */
#define ACMP_ACMP3_CFG_FLT_SAMPLE_Pos     (8UL)                     /*!< FLT_SAMPLE (Bit 8)                                    */
#define ACMP_ACMP3_CFG_FLT_SAMPLE_Msk     (0x300UL)                 /*!< FLT_SAMPLE (Bitfield-Mask: 0x03)                      */
#define ACMP_ACMP3_CFG_HYS_EN_Pos         (6UL)                     /*!< HYS_EN (Bit 6)                                        */
#define ACMP_ACMP3_CFG_HYS_EN_Msk         (0x40UL)                  /*!< HYS_EN (Bitfield-Mask: 0x01)                          */
#define ACMP_ACMP3_CFG_INT_TYPE_Pos       (4UL)                     /*!< INT_TYPE (Bit 4)                                      */
#define ACMP_ACMP3_CFG_INT_TYPE_Msk       (0x30UL)                  /*!< INT_TYPE (Bitfield-Mask: 0x03)                        */
#define ACMP_ACMP3_CFG_IE_Pos             (3UL)                     /*!< IE (Bit 3)                                            */
#define ACMP_ACMP3_CFG_IE_Msk             (0x8UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
#define ACMP_ACMP3_CFG_POL_Pos            (1UL)                     /*!< POL (Bit 1)                                           */
#define ACMP_ACMP3_CFG_POL_Msk            (0x2UL)                   /*!< POL (Bitfield-Mask: 0x01)                             */
#define ACMP_ACMP3_CFG_EN_Pos             (0UL)                     /*!< EN (Bit 0)                                            */
#define ACMP_ACMP3_CFG_EN_Msk             (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */


/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define FLASH_CR_KEY_Pos                  (16UL)                    /*!< KEY (Bit 16)                                          */
#define FLASH_CR_KEY_Msk                  (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define FLASH_CR_PF_EN_Pos                (6UL)                     /*!< PF_EN (Bit 6)                                         */
#define FLASH_CR_PF_EN_Msk                (0x40UL)                  /*!< PF_EN (Bitfield-Mask: 0x01)                           */
#define FLASH_CR_WS_Pos                   (4UL)                     /*!< WS (Bit 4)                                            */
#define FLASH_CR_WS_Msk                   (0x30UL)                  /*!< WS (Bitfield-Mask: 0x03)                              */
#define FLASH_CR_OP_MODE_Pos              (1UL)                     /*!< OP_MODE (Bit 1)                                       */
#define FLASH_CR_OP_MODE_Msk              (0xeUL)                   /*!< OP_MODE (Bitfield-Mask: 0x07)                         */
#define FLASH_CR_OP_START_Pos             (0UL)                     /*!< OP_START (Bit 0)                                      */
#define FLASH_CR_OP_START_Msk             (0x1UL)                   /*!< OP_START (Bitfield-Mask: 0x01)                        */
/* =========================================================  ADDR  ========================================================== */
#define FLASH_ADDR_ADDR_Pos               (0UL)                     /*!< ADDR (Bit 0)                                          */
#define FLASH_ADDR_ADDR_Msk               (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DATA  ========================================================== */
#define FLASH_DATA_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define FLASH_DATA_DATA_Msk               (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  CR_LOCK  ======================================================== */
#define FLASH_CR_LOCK_KEY_Pos             (16UL)                    /*!< KEY (Bit 16)                                          */
#define FLASH_CR_LOCK_KEY_Msk             (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define FLASH_CR_LOCK_LK_Pos              (0UL)                     /*!< LK (Bit 0)                                            */
#define FLASH_CR_LOCK_LK_Msk              (0x1UL)                   /*!< LK (Bitfield-Mask: 0x01)                              */
/* ==========================================================  SR  =========================================================== */
#define FLASH_SR_ADDR_ERR_Pos             (6UL)                     /*!< ADDR_ERR (Bit 6)                                      */
#define FLASH_SR_ADDR_ERR_Msk             (0x40UL)                  /*!< ADDR_ERR (Bitfield-Mask: 0x01)                        */
#define FLASH_SR_OP_WP_ERR_Pos            (5UL)                     /*!< OP_WP_ERR (Bit 5)                                     */
#define FLASH_SR_OP_WP_ERR_Msk            (0x20UL)                  /*!< OP_WP_ERR (Bitfield-Mask: 0x01)                       */
#define FLASH_SR_MN_WP_ERR_Pos            (4UL)                     /*!< MN_WP_ERR (Bit 4)                                     */
#define FLASH_SR_MN_WP_ERR_Msk            (0x10UL)                  /*!< MN_WP_ERR (Bitfield-Mask: 0x01)                       */
#define FLASH_SR_CPE_WP_ERR_Pos           (3UL)                     /*!< CPE_WP_ERR (Bit 3)                                    */
#define FLASH_SR_CPE_WP_ERR_Msk           (0x8UL)                   /*!< CPE_WP_ERR (Bitfield-Mask: 0x01)                      */
#define FLASH_SR_CR_LK_ERR_Pos            (2UL)                     /*!< CR_LK_ERR (Bit 2)                                     */
#define FLASH_SR_CR_LK_ERR_Msk            (0x4UL)                   /*!< CR_LK_ERR (Bitfield-Mask: 0x01)                       */
#define FLASH_SR_CR_BSY_ERR_Pos           (1UL)                     /*!< CR_BSY_ERR (Bit 1)                                    */
#define FLASH_SR_CR_BSY_ERR_Msk           (0x2UL)                   /*!< CR_BSY_ERR (Bitfield-Mask: 0x01)                      */
#define FLASH_SR_BUSY_Pos                 (0UL)                     /*!< BUSY (Bit 0)                                          */
#define FLASH_SR_BUSY_Msk                 (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
/* ========================================================  FAC_REC  ======================================================== */
#define FLASH_FAC_REC_KEY_Pos             (16UL)                    /*!< KEY (Bit 16)                                          */
#define FLASH_FAC_REC_KEY_Msk             (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define FLASH_FAC_REC_UNLK_DATA_Pos       (0UL)                     /*!< UNLK_DATA (Bit 0)                                     */
#define FLASH_FAC_REC_UNLK_DATA_Msk       (0xffffUL)                /*!< UNLK_DATA (Bitfield-Mask: 0xffff)                     */


/* =========================================================================================================================== */
/* ================                                            PVD                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define PVD_CR_IE_Pos                     (13UL)                    /*!< IE (Bit 13)                                           */
#define PVD_CR_IE_Msk                     (0x2000UL)                /*!< IE (Bitfield-Mask: 0x01)                              */
#define PVD_CR_FLT_EN_Pos                 (12UL)                    /*!< FLT_EN (Bit 12)                                       */
#define PVD_CR_FLT_EN_Msk                 (0x1000UL)                /*!< FLT_EN (Bitfield-Mask: 0x01)                          */
#define PVD_CR_FLT_LEN_Pos                (10UL)                    /*!< FLT_LEN (Bit 10)                                      */
#define PVD_CR_FLT_LEN_Msk                (0xc00UL)                 /*!< FLT_LEN (Bitfield-Mask: 0x03)                         */
#define PVD_CR_FLT_SAMPLE_Pos             (8UL)                     /*!< FLT_SAMPLE (Bit 8)                                    */
#define PVD_CR_FLT_SAMPLE_Msk             (0x300UL)                 /*!< FLT_SAMPLE (Bitfield-Mask: 0x03)                      */
#define PVD_CR_REF_SEL_Pos                (4UL)                     /*!< REF_SEL (Bit 4)                                       */
#define PVD_CR_REF_SEL_Msk                (0xf0UL)                  /*!< REF_SEL (Bitfield-Mask: 0x0f)                         */
#define PVD_CR_TRIG_RESULT_Pos            (3UL)                     /*!< TRIG_RESULT (Bit 3)                                   */
#define PVD_CR_TRIG_RESULT_Msk            (0x8UL)                   /*!< TRIG_RESULT (Bitfield-Mask: 0x01)                     */
#define PVD_CR_TRIG_TYPE_Pos              (1UL)                     /*!< TRIG_TYPE (Bit 1)                                     */
#define PVD_CR_TRIG_TYPE_Msk              (0x6UL)                   /*!< TRIG_TYPE (Bitfield-Mask: 0x03)                       */
#define PVD_CR_EN_Pos                     (0UL)                     /*!< EN (Bit 0)                                            */
#define PVD_CR_EN_Msk                     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  SR  =========================================================== */
#define PVD_SR_RDY_Pos                    (2UL)                     /*!< RDY (Bit 2)                                           */
#define PVD_SR_RDY_Msk                    (0x4UL)                   /*!< RDY (Bitfield-Mask: 0x01)                             */
#define PVD_SR_RES_Pos                    (1UL)                     /*!< RES (Bit 1)                                           */
#define PVD_SR_RES_Msk                    (0x2UL)                   /*!< RES (Bitfield-Mask: 0x01)                             */
#define PVD_SR_IF_Pos                     (0UL)                     /*!< IF (Bit 0)                                            */
#define PVD_SR_IF_Msk                     (0x1UL)                   /*!< IF (Bitfield-Mask: 0x01)                              */


/* =========================================================================================================================== */
/* ================                                         CAN_BASE                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define CAN_BASE_CTRL_OVRRHIE_Pos         (8UL)                     /*!< OVRRHIE (Bit 8)                                       */
#define CAN_BASE_CTRL_OVRRHIE_Msk         (0x100UL)                 /*!< OVRRHIE (Bitfield-Mask: 0x01)                         */
#define CAN_BASE_CTRL_EN_Pos              (6UL)                     /*!< EN (Bit 6)                                            */
#define CAN_BASE_CTRL_EN_Msk              (0x40UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define CAN_BASE_CTRL_OIE_Pos             (4UL)                     /*!< OIE (Bit 4)                                           */
#define CAN_BASE_CTRL_OIE_Msk             (0x10UL)                  /*!< OIE (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_CTRL_EIE_Pos             (3UL)                     /*!< EIE (Bit 3)                                           */
#define CAN_BASE_CTRL_EIE_Msk             (0x8UL)                   /*!< EIE (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_CTRL_TIE_Pos             (2UL)                     /*!< TIE (Bit 2)                                           */
#define CAN_BASE_CTRL_TIE_Msk             (0x4UL)                   /*!< TIE (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_CTRL_RIE_Pos             (1UL)                     /*!< RIE (Bit 1)                                           */
#define CAN_BASE_CTRL_RIE_Msk             (0x2UL)                   /*!< RIE (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_CTRL_RM_Pos              (0UL)                     /*!< RM (Bit 0)                                            */
#define CAN_BASE_CTRL_RM_Msk              (0x1UL)                   /*!< RM (Bitfield-Mask: 0x01)                              */
/* ========================================================  COMMAND  ======================================================== */
#define CAN_BASE_COMMAND_CDO_Pos          (3UL)                     /*!< CDO (Bit 3)                                           */
#define CAN_BASE_COMMAND_CDO_Msk          (0x8UL)                   /*!< CDO (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_COMMAND_RRB_Pos          (2UL)                     /*!< RRB (Bit 2)                                           */
#define CAN_BASE_COMMAND_RRB_Msk          (0x4UL)                   /*!< RRB (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_COMMAND_AT_Pos           (1UL)                     /*!< AT (Bit 1)                                            */
#define CAN_BASE_COMMAND_AT_Msk           (0x2UL)                   /*!< AT (Bitfield-Mask: 0x01)                              */
#define CAN_BASE_COMMAND_TR_Pos           (0UL)                     /*!< TR (Bit 0)                                            */
#define CAN_BASE_COMMAND_TR_Msk           (0x1UL)                   /*!< TR (Bitfield-Mask: 0x01)                              */
/* ========================================================  STATUS  ========================================================= */
#define CAN_BASE_STATUS_OVRROS_Pos        (8UL)                     /*!< OVRROS (Bit 8)                                        */
#define CAN_BASE_STATUS_OVRROS_Msk        (0x100UL)                 /*!< OVRROS (Bitfield-Mask: 0x01)                          */
#define CAN_BASE_STATUS_BS_Pos            (7UL)                     /*!< BS (Bit 7)                                            */
#define CAN_BASE_STATUS_BS_Msk            (0x80UL)                  /*!< BS (Bitfield-Mask: 0x01)                              */
#define CAN_BASE_STATUS_ES_Pos            (6UL)                     /*!< ES (Bit 6)                                            */
#define CAN_BASE_STATUS_ES_Msk            (0x40UL)                  /*!< ES (Bitfield-Mask: 0x01)                              */
#define CAN_BASE_STATUS_TS_Pos            (5UL)                     /*!< TS (Bit 5)                                            */
#define CAN_BASE_STATUS_TS_Msk            (0x20UL)                  /*!< TS (Bitfield-Mask: 0x01)                              */
#define CAN_BASE_STATUS_RS_Pos            (4UL)                     /*!< RS (Bit 4)                                            */
#define CAN_BASE_STATUS_RS_Msk            (0x10UL)                  /*!< RS (Bitfield-Mask: 0x01)                              */
#define CAN_BASE_STATUS_TCS_Pos           (3UL)                     /*!< TCS (Bit 3)                                           */
#define CAN_BASE_STATUS_TCS_Msk           (0x8UL)                   /*!< TCS (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_STATUS_TBS_Pos           (2UL)                     /*!< TBS (Bit 2)                                           */
#define CAN_BASE_STATUS_TBS_Msk           (0x4UL)                   /*!< TBS (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_STATUS_DOS_Pos           (1UL)                     /*!< DOS (Bit 1)                                           */
#define CAN_BASE_STATUS_DOS_Msk           (0x2UL)                   /*!< DOS (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_STATUS_RBS_Pos           (0UL)                     /*!< RBS (Bit 0)                                           */
#define CAN_BASE_STATUS_RBS_Msk           (0x1UL)                   /*!< RBS (Bitfield-Mask: 0x01)                             */
/* =======================================================  INTERRUPT  ======================================================= */
#define CAN_BASE_INTERRUPT_OVRROI_Pos     (8UL)                     /*!< OVRROI (Bit 8)                                        */
#define CAN_BASE_INTERRUPT_OVRROI_Msk     (0x100UL)                 /*!< OVRROI (Bitfield-Mask: 0x01)                          */
#define CAN_BASE_INTERRUPT_DOI_Pos        (3UL)                     /*!< DOI (Bit 3)                                           */
#define CAN_BASE_INTERRUPT_DOI_Msk        (0x8UL)                   /*!< DOI (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_INTERRUPT_EI_Pos         (2UL)                     /*!< EI (Bit 2)                                            */
#define CAN_BASE_INTERRUPT_EI_Msk         (0x4UL)                   /*!< EI (Bitfield-Mask: 0x01)                              */
#define CAN_BASE_INTERRUPT_TI_Pos         (1UL)                     /*!< TI (Bit 1)                                            */
#define CAN_BASE_INTERRUPT_TI_Msk         (0x2UL)                   /*!< TI (Bitfield-Mask: 0x01)                              */
#define CAN_BASE_INTERRUPT_RI_Pos         (0UL)                     /*!< RI (Bit 0)                                            */
#define CAN_BASE_INTERRUPT_RI_Msk         (0x1UL)                   /*!< RI (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ACR  ========================================================== */
#define CAN_BASE_ACR_AC_Pos               (0UL)                     /*!< AC (Bit 0)                                            */
#define CAN_BASE_ACR_AC_Msk               (0xffUL)                  /*!< AC (Bitfield-Mask: 0xff)                              */
/* ==========================================================  AMR  ========================================================== */
#define CAN_BASE_AMR_AM_Pos               (0UL)                     /*!< AM (Bit 0)                                            */
#define CAN_BASE_AMR_AM_Msk               (0xffUL)                  /*!< AM (Bitfield-Mask: 0xff)                              */
/* =========================================================  BTR0  ========================================================== */
#define CAN_BASE_BTR0_SJW_Pos             (8UL)                     /*!< SJW (Bit 8)                                           */
#define CAN_BASE_BTR0_SJW_Msk             (0x300UL)                 /*!< SJW (Bitfield-Mask: 0x03)                             */
#define CAN_BASE_BTR0_BRP_Pos             (0UL)                     /*!< BRP (Bit 0)                                           */
#define CAN_BASE_BTR0_BRP_Msk             (0xffUL)                  /*!< BRP (Bitfield-Mask: 0xff)                             */
/* =========================================================  BTR1  ========================================================== */
#define CAN_BASE_BTR1_SAM_Pos             (7UL)                     /*!< SAM (Bit 7)                                           */
#define CAN_BASE_BTR1_SAM_Msk             (0x80UL)                  /*!< SAM (Bitfield-Mask: 0x01)                             */
#define CAN_BASE_BTR1_TSEG2_Pos           (4UL)                     /*!< TSEG2 (Bit 4)                                         */
#define CAN_BASE_BTR1_TSEG2_Msk           (0x70UL)                  /*!< TSEG2 (Bitfield-Mask: 0x03)                           */
#define CAN_BASE_BTR1_TSEG1_Pos           (0UL)                     /*!< TSEG1 (Bit 0)                                         */
#define CAN_BASE_BTR1_TSEG1_Msk           (0xfUL)                   /*!< TSEG1 (Bitfield-Mask: 0x0f)                           */
/* ======================================================  TX_ID_BYTE1  ====================================================== */
#define CAN_BASE_TX_ID_BYTE1_TX_ID1_Pos   (0UL)                     /*!< TX_ID1 (Bit 0)                                        */
#define CAN_BASE_TX_ID_BYTE1_TX_ID1_Msk   (0xffUL)                  /*!< TX_ID1 (Bitfield-Mask: 0xff)                          */
/* ======================================================  TX_ID_BYTE2  ====================================================== */
#define CAN_BASE_TX_ID_BYTE2_TX_ID2_Pos   (5UL)                     /*!< TX_ID2 (Bit 5)                                        */
#define CAN_BASE_TX_ID_BYTE2_TX_ID2_Msk   (0xe0UL)                  /*!< TX_ID2 (Bitfield-Mask: 0x07)                          */
#define CAN_BASE_TX_ID_BYTE2_TX_RTR_Pos   (4UL)                     /*!< TX_RTR (Bit 4)                                        */
#define CAN_BASE_TX_ID_BYTE2_TX_RTR_Msk   (0x10UL)                  /*!< TX_RTR (Bitfield-Mask: 0x01)                          */
#define CAN_BASE_TX_ID_BYTE2_TX_DLC_Pos   (0UL)                     /*!< TX_DLC (Bit 0)                                        */
#define CAN_BASE_TX_ID_BYTE2_TX_DLC_Msk   (0xfUL)                   /*!< TX_DLC (Bitfield-Mask: 0x0f)                          */
/* =======================================================  TX_DATA1  ======================================================== */
#define CAN_BASE_TX_DATA1_TX_DATA_Pos     (0UL)                     /*!< TX_DATA (Bit 0)                                       */
#define CAN_BASE_TX_DATA1_TX_DATA_Msk     (0xffUL)                  /*!< TX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  TX_DATA2  ======================================================== */
#define CAN_BASE_TX_DATA2_TX_DATA_Pos     (0UL)                     /*!< TX_DATA (Bit 0)                                       */
#define CAN_BASE_TX_DATA2_TX_DATA_Msk     (0xffUL)                  /*!< TX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  TX_DATA3  ======================================================== */
#define CAN_BASE_TX_DATA3_TX_DATA_Pos     (0UL)                     /*!< TX_DATA (Bit 0)                                       */
#define CAN_BASE_TX_DATA3_TX_DATA_Msk     (0xffUL)                  /*!< TX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  TX_DATA4  ======================================================== */
#define CAN_BASE_TX_DATA4_TX_DATA_Pos     (0UL)                     /*!< TX_DATA (Bit 0)                                       */
#define CAN_BASE_TX_DATA4_TX_DATA_Msk     (0xffUL)                  /*!< TX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  TX_DATA5  ======================================================== */
#define CAN_BASE_TX_DATA5_TX_DATA_Pos     (0UL)                     /*!< TX_DATA (Bit 0)                                       */
#define CAN_BASE_TX_DATA5_TX_DATA_Msk     (0xffUL)                  /*!< TX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  TX_DATA6  ======================================================== */
#define CAN_BASE_TX_DATA6_TX_DATA_Pos     (0UL)                     /*!< TX_DATA (Bit 0)                                       */
#define CAN_BASE_TX_DATA6_TX_DATA_Msk     (0xffUL)                  /*!< TX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  TX_DATA7  ======================================================== */
#define CAN_BASE_TX_DATA7_TX_DATA_Pos     (0UL)                     /*!< TX_DATA (Bit 0)                                       */
#define CAN_BASE_TX_DATA7_TX_DATA_Msk     (0xffUL)                  /*!< TX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  TX_DATA8  ======================================================== */
#define CAN_BASE_TX_DATA8_TX_DATA_Pos     (0UL)                     /*!< TX_DATA (Bit 0)                                       */
#define CAN_BASE_TX_DATA8_TX_DATA_Msk     (0xffUL)                  /*!< TX_DATA (Bitfield-Mask: 0xff)                         */
/* ========================================================  RX_ID1  ========================================================= */
#define CAN_BASE_RX_ID1_RX_ID1_Pos        (0UL)                     /*!< RX_ID1 (Bit 0)                                        */
#define CAN_BASE_RX_ID1_RX_ID1_Msk        (0xffUL)                  /*!< RX_ID1 (Bitfield-Mask: 0xff)                          */
/* ======================================================  RX_ID_BYTE2  ====================================================== */
#define CAN_BASE_RX_ID_BYTE2_RX_ID2_Pos   (5UL)                     /*!< RX_ID2 (Bit 5)                                        */
#define CAN_BASE_RX_ID_BYTE2_RX_ID2_Msk   (0xe0UL)                  /*!< RX_ID2 (Bitfield-Mask: 0x07)                          */
#define CAN_BASE_RX_ID_BYTE2_RX_RTR_Pos   (4UL)                     /*!< RX_RTR (Bit 4)                                        */
#define CAN_BASE_RX_ID_BYTE2_RX_RTR_Msk   (0x10UL)                  /*!< RX_RTR (Bitfield-Mask: 0x01)                          */
#define CAN_BASE_RX_ID_BYTE2_RX_DLC_Pos   (0UL)                     /*!< RX_DLC (Bit 0)                                        */
#define CAN_BASE_RX_ID_BYTE2_RX_DLC_Msk   (0xfUL)                   /*!< RX_DLC (Bitfield-Mask: 0x0f)                          */
/* =======================================================  RX_DATA1  ======================================================== */
#define CAN_BASE_RX_DATA1_RX_DATA_Pos     (0UL)                     /*!< RX_DATA (Bit 0)                                       */
#define CAN_BASE_RX_DATA1_RX_DATA_Msk     (0xffUL)                  /*!< RX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  RX_DATA2  ======================================================== */
#define CAN_BASE_RX_DATA2_RX_DATA_Pos     (0UL)                     /*!< RX_DATA (Bit 0)                                       */
#define CAN_BASE_RX_DATA2_RX_DATA_Msk     (0xffUL)                  /*!< RX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  RX_DATA3  ======================================================== */
#define CAN_BASE_RX_DATA3_RX_DATA_Pos     (0UL)                     /*!< RX_DATA (Bit 0)                                       */
#define CAN_BASE_RX_DATA3_RX_DATA_Msk     (0xffUL)                  /*!< RX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  RX_DATA4  ======================================================== */
#define CAN_BASE_RX_DATA4_RX_DATA_Pos     (0UL)                     /*!< RX_DATA (Bit 0)                                       */
#define CAN_BASE_RX_DATA4_RX_DATA_Msk     (0xffUL)                  /*!< RX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  RX_DATA5  ======================================================== */
#define CAN_BASE_RX_DATA5_RX_DATA_Pos     (0UL)                     /*!< RX_DATA (Bit 0)                                       */
#define CAN_BASE_RX_DATA5_RX_DATA_Msk     (0xffUL)                  /*!< RX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  RX_DATA6  ======================================================== */
#define CAN_BASE_RX_DATA6_RX_DATA_Pos     (0UL)                     /*!< RX_DATA (Bit 0)                                       */
#define CAN_BASE_RX_DATA6_RX_DATA_Msk     (0xffUL)                  /*!< RX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  RX_DATA7  ======================================================== */
#define CAN_BASE_RX_DATA7_RX_DATA_Pos     (0UL)                     /*!< RX_DATA (Bit 0)                                       */
#define CAN_BASE_RX_DATA7_RX_DATA_Msk     (0xffUL)                  /*!< RX_DATA (Bitfield-Mask: 0xff)                         */
/* =======================================================  RX_DATA8  ======================================================== */
#define CAN_BASE_RX_DATA8_RX_DATA_Pos     (0UL)                     /*!< RX_DATA (Bit 0)                                       */
#define CAN_BASE_RX_DATA8_RX_DATA_Msk     (0xffUL)                  /*!< RX_DATA (Bitfield-Mask: 0xff)                         */
/* ========================================================  EX_CAN  ========================================================= */
#define CAN_BASE_EX_CAN_EX_CAN_Pos        (7UL)                     /*!< EX_CAN (Bit 7)                                        */
#define CAN_BASE_EX_CAN_EX_CAN_Msk        (0x80UL)                  /*!< EX_CAN (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                         CAN_PELI                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  MODE  ========================================================== */
#define CAN_PELI_MODE_EN_Pos              (6UL)                     /*!< EN (Bit 6)                                            */
#define CAN_PELI_MODE_EN_Msk              (0x40UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define CAN_PELI_MODE_AFM_Pos             (3UL)                     /*!< AFM (Bit 3)                                           */
#define CAN_PELI_MODE_AFM_Msk             (0x8UL)                   /*!< AFM (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_MODE_STM_Pos             (2UL)                     /*!< STM (Bit 2)                                           */
#define CAN_PELI_MODE_STM_Msk             (0x4UL)                   /*!< STM (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_MODE_LOM_Pos             (1UL)                     /*!< LOM (Bit 1)                                           */
#define CAN_PELI_MODE_LOM_Msk             (0x2UL)                   /*!< LOM (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_MODE_RM_Pos              (0UL)                     /*!< RM (Bit 0)                                            */
#define CAN_PELI_MODE_RM_Msk              (0x1UL)                   /*!< RM (Bitfield-Mask: 0x01)                              */
/* ========================================================  COMMAND  ======================================================== */
#define CAN_PELI_COMMAND_SRR_Pos          (4UL)                     /*!< SRR (Bit 4)                                           */
#define CAN_PELI_COMMAND_SRR_Msk          (0x10UL)                  /*!< SRR (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_COMMAND_CDO_Pos          (3UL)                     /*!< CDO (Bit 3)                                           */
#define CAN_PELI_COMMAND_CDO_Msk          (0x8UL)                   /*!< CDO (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_COMMAND_RRB_Pos          (2UL)                     /*!< RRB (Bit 2)                                           */
#define CAN_PELI_COMMAND_RRB_Msk          (0x4UL)                   /*!< RRB (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_COMMAND_AT_Pos           (1UL)                     /*!< AT (Bit 1)                                            */
#define CAN_PELI_COMMAND_AT_Msk           (0x2UL)                   /*!< AT (Bitfield-Mask: 0x01)                              */
#define CAN_PELI_COMMAND_TR_Pos           (0UL)                     /*!< TR (Bit 0)                                            */
#define CAN_PELI_COMMAND_TR_Msk           (0x1UL)                   /*!< TR (Bitfield-Mask: 0x01)                              */
/* ========================================================  STATUS  ========================================================= */
#define CAN_PELI_STATUS_OVRROS_Pos        (8UL)                     /*!< OVRROS (Bit 8)                                        */
#define CAN_PELI_STATUS_OVRROS_Msk        (0x100UL)                 /*!< OVRROS (Bitfield-Mask: 0x01)                          */
#define CAN_PELI_STATUS_BS_Pos            (7UL)                     /*!< BS (Bit 7)                                            */
#define CAN_PELI_STATUS_BS_Msk            (0x80UL)                  /*!< BS (Bitfield-Mask: 0x01)                              */
#define CAN_PELI_STATUS_ES_Pos            (6UL)                     /*!< ES (Bit 6)                                            */
#define CAN_PELI_STATUS_ES_Msk            (0x40UL)                  /*!< ES (Bitfield-Mask: 0x01)                              */
#define CAN_PELI_STATUS_TS_Pos            (5UL)                     /*!< TS (Bit 5)                                            */
#define CAN_PELI_STATUS_TS_Msk            (0x20UL)                  /*!< TS (Bitfield-Mask: 0x01)                              */
#define CAN_PELI_STATUS_RS_Pos            (4UL)                     /*!< RS (Bit 4)                                            */
#define CAN_PELI_STATUS_RS_Msk            (0x10UL)                  /*!< RS (Bitfield-Mask: 0x01)                              */
#define CAN_PELI_STATUS_TCS_Pos           (3UL)                     /*!< TCS (Bit 3)                                           */
#define CAN_PELI_STATUS_TCS_Msk           (0x8UL)                   /*!< TCS (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_STATUS_TBS_Pos           (2UL)                     /*!< TBS (Bit 2)                                           */
#define CAN_PELI_STATUS_TBS_Msk           (0x4UL)                   /*!< TBS (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_STATUS_DOS_Pos           (1UL)                     /*!< DOS (Bit 1)                                           */
#define CAN_PELI_STATUS_DOS_Msk           (0x2UL)                   /*!< DOS (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_STATUS_RBS_Pos           (0UL)                     /*!< RBS (Bit 0)                                           */
#define CAN_PELI_STATUS_RBS_Msk           (0x1UL)                   /*!< RBS (Bitfield-Mask: 0x01)                             */
/* =======================================================  INTERRUPT  ======================================================= */
#define CAN_PELI_INTERRUPT_OVRROI_Pos     (8UL)                     /*!< OVRROI (Bit 8)                                        */
#define CAN_PELI_INTERRUPT_OVRROI_Msk     (0x100UL)                 /*!< OVRROI (Bitfield-Mask: 0x01)                          */
#define CAN_PELI_INTERRUPT_BEI_Pos        (7UL)                     /*!< BEI (Bit 7)                                           */
#define CAN_PELI_INTERRUPT_BEI_Msk        (0x80UL)                  /*!< BEI (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_INTERRUPT_ALI_Pos        (6UL)                     /*!< ALI (Bit 6)                                           */
#define CAN_PELI_INTERRUPT_ALI_Msk        (0x40UL)                  /*!< ALI (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_INTERRUPT_EPI_Pos        (5UL)                     /*!< EPI (Bit 5)                                           */
#define CAN_PELI_INTERRUPT_EPI_Msk        (0x20UL)                  /*!< EPI (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_INTERRUPT_DOI_Pos        (3UL)                     /*!< DOI (Bit 3)                                           */
#define CAN_PELI_INTERRUPT_DOI_Msk        (0x8UL)                   /*!< DOI (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_INTERRUPT_EI_Pos         (2UL)                     /*!< EI (Bit 2)                                            */
#define CAN_PELI_INTERRUPT_EI_Msk         (0x4UL)                   /*!< EI (Bitfield-Mask: 0x01)                              */
#define CAN_PELI_INTERRUPT_TI_Pos         (1UL)                     /*!< TI (Bit 1)                                            */
#define CAN_PELI_INTERRUPT_TI_Msk         (0x2UL)                   /*!< TI (Bitfield-Mask: 0x01)                              */
#define CAN_PELI_INTERRUPT_RI_Pos         (0UL)                     /*!< RI (Bit 0)                                            */
#define CAN_PELI_INTERRUPT_RI_Msk         (0x1UL)                   /*!< RI (Bitfield-Mask: 0x01)                              */
/* ==========================================================  IE  =========================================================== */
#define CAN_PELI_IE_OVRRHIE_Pos           (8UL)                     /*!< OVRRHIE (Bit 8)                                       */
#define CAN_PELI_IE_OVRRHIE_Msk           (0x100UL)                 /*!< OVRRHIE (Bitfield-Mask: 0x01)                         */
#define CAN_PELI_IE_BEIE_Pos              (7UL)                     /*!< BEIE (Bit 7)                                          */
#define CAN_PELI_IE_BEIE_Msk              (0x80UL)                  /*!< BEIE (Bitfield-Mask: 0x01)                            */
#define CAN_PELI_IE_ALIE_Pos              (6UL)                     /*!< ALIE (Bit 6)                                          */
#define CAN_PELI_IE_ALIE_Msk              (0x40UL)                  /*!< ALIE (Bitfield-Mask: 0x01)                            */
#define CAN_PELI_IE_EPIE_Pos              (5UL)                     /*!< EPIE (Bit 5)                                          */
#define CAN_PELI_IE_EPIE_Msk              (0x20UL)                  /*!< EPIE (Bitfield-Mask: 0x01)                            */
#define CAN_PELI_IE_DOIE_Pos              (3UL)                     /*!< DOIE (Bit 3)                                          */
#define CAN_PELI_IE_DOIE_Msk              (0x8UL)                   /*!< DOIE (Bitfield-Mask: 0x01)                            */
#define CAN_PELI_IE_EIE_Pos               (2UL)                     /*!< EIE (Bit 2)                                           */
#define CAN_PELI_IE_EIE_Msk               (0x4UL)                   /*!< EIE (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_IE_TIE_Pos               (1UL)                     /*!< TIE (Bit 1)                                           */
#define CAN_PELI_IE_TIE_Msk               (0x2UL)                   /*!< TIE (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_IE_RIE_Pos               (0UL)                     /*!< RIE (Bit 0)                                           */
#define CAN_PELI_IE_RIE_Msk               (0x1UL)                   /*!< RIE (Bitfield-Mask: 0x01)                             */
/* =========================================================  BTR0  ========================================================== */
#define CAN_PELI_BTR0_SJW_Pos             (8UL)                     /*!< SJW (Bit 8)                                           */
#define CAN_PELI_BTR0_SJW_Msk             (0x300UL)                 /*!< SJW (Bitfield-Mask: 0x03)                             */
#define CAN_PELI_BTR0_BRP_Pos             (0UL)                     /*!< BRP (Bit 0)                                           */
#define CAN_PELI_BTR0_BRP_Msk             (0xffUL)                  /*!< BRP (Bitfield-Mask: 0xff)                             */
/* =========================================================  BTR1  ========================================================== */
#define CAN_PELI_BTR1_SAM_Pos             (7UL)                     /*!< SAM (Bit 7)                                           */
#define CAN_PELI_BTR1_SAM_Msk             (0x80UL)                  /*!< SAM (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_BTR1_TSEG2_Pos           (4UL)                     /*!< TSEG2 (Bit 4)                                         */
#define CAN_PELI_BTR1_TSEG2_Msk           (0x70UL)                  /*!< TSEG2 (Bitfield-Mask: 0x03)                           */
#define CAN_PELI_BTR1_TSEG1_Pos           (0UL)                     /*!< TSEG1 (Bit 0)                                         */
#define CAN_PELI_BTR1_TSEG1_Msk           (0xfUL)                   /*!< TSEG1 (Bitfield-Mask: 0x0f)                           */
/* ==========================================================  ALC  ========================================================== */
#define CAN_PELI_ALC_ALC_Pos              (0UL)                     /*!< ALC (Bit 0)                                           */
#define CAN_PELI_ALC_ALC_Msk              (0x1fUL)                  /*!< ALC (Bitfield-Mask: 0x1f)                             */
/* ==========================================================  ECC  ========================================================== */
#define CAN_PELI_ECC_ERRC_Pos             (6UL)                     /*!< ERRC (Bit 6)                                          */
#define CAN_PELI_ECC_ERRC_Msk             (0xc0UL)                  /*!< ERRC (Bitfield-Mask: 0x03)                            */
#define CAN_PELI_ECC_DIR_Pos              (5UL)                     /*!< DIR (Bit 5)                                           */
#define CAN_PELI_ECC_DIR_Msk              (0x20UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_ECC_SEG_Pos              (0UL)                     /*!< SEG (Bit 0)                                           */
#define CAN_PELI_ECC_SEG_Msk              (0x1fUL)                  /*!< SEG (Bitfield-Mask: 0x1f)                             */
/* ==========================================================  EWL  ========================================================== */
#define CAN_PELI_EWL_EWL_Pos              (0UL)                     /*!< EWL (Bit 0)                                           */
#define CAN_PELI_EWL_EWL_Msk              (0xffUL)                  /*!< EWL (Bitfield-Mask: 0xff)                             */
/* ========================================================  RX_ERR  ========================================================= */
#define CAN_PELI_RX_ERR_RX_ERR_Pos        (0UL)                     /*!< RX_ERR (Bit 0)                                        */
#define CAN_PELI_RX_ERR_RX_ERR_Msk        (0xffUL)                  /*!< RX_ERR (Bitfield-Mask: 0xff)                          */
/* ========================================================  TX_ERR  ========================================================= */
#define CAN_PELI_TX_ERR_TX_ERR_Pos        (0UL)                     /*!< TX_ERR (Bit 0)                                        */
#define CAN_PELI_TX_ERR_TX_ERR_Msk        (0xffUL)                  /*!< TX_ERR (Bitfield-Mask: 0xff)                          */
/* ==========================================================  SFF  ========================================================== */
#define CAN_PELI_SFF_FF_Pos               (7UL)                     /*!< FF (Bit 7)                                            */
#define CAN_PELI_SFF_FF_Msk               (0x80UL)                  /*!< FF (Bitfield-Mask: 0x01)                              */
#define CAN_PELI_SFF_RTR_Pos              (6UL)                     /*!< RTR (Bit 6)                                           */
#define CAN_PELI_SFF_RTR_Msk              (0x40UL)                  /*!< RTR (Bitfield-Mask: 0x01)                             */
#define CAN_PELI_SFF_DLC_Pos              (0UL)                     /*!< DLC (Bit 0)                                           */
#define CAN_PELI_SFF_DLC_Msk              (0xfUL)                   /*!< DLC (Bitfield-Mask: 0x0f)                             */
/* ==========================================================  ID1  ========================================================== */
#define CAN_PELI_ID1_ID1_Pos              (0UL)                     /*!< ID1 (Bit 0)                                           */
#define CAN_PELI_ID1_ID1_Msk              (0xffUL)                  /*!< ID1 (Bitfield-Mask: 0xff)                             */
/* ==========================================================  ID2  ========================================================== */
#define CAN_PELI_ID2_ID2_Pos              (0UL)                     /*!< ID2 (Bit 0)                                           */
#define CAN_PELI_ID2_ID2_Msk              (0xffUL)                  /*!< ID2 (Bitfield-Mask: 0xff)                             */
/* =======================================================  DATA1_ID3  ======================================================= */
#define CAN_PELI_DATA1_ID3_DATA1_ID3_Pos  (0UL)                     /*!< DATA1_ID3 (Bit 0)                                     */
#define CAN_PELI_DATA1_ID3_DATA1_ID3_Msk  (0xffUL)                  /*!< DATA1_ID3 (Bitfield-Mask: 0xff)                       */
/* =======================================================  DATA2_ID4  ======================================================= */
#define CAN_PELI_DATA2_ID4_DATA2_ID4_Pos  (0UL)                     /*!< DATA2_ID4 (Bit 0)                                     */
#define CAN_PELI_DATA2_ID4_DATA2_ID4_Msk  (0xffUL)                  /*!< DATA2_ID4 (Bitfield-Mask: 0xff)                       */
/* =======================================================  DATA3_DA1  ======================================================= */
#define CAN_PELI_DATA3_DA1_DATA3_DA1_Pos  (0UL)                     /*!< DATA3_DA1 (Bit 0)                                     */
#define CAN_PELI_DATA3_DA1_DATA3_DA1_Msk  (0xffUL)                  /*!< DATA3_DA1 (Bitfield-Mask: 0xff)                       */
/* =======================================================  DATA4_DA2  ======================================================= */
#define CAN_PELI_DATA4_DA2_DATA4_DA2_Pos  (0UL)                     /*!< DATA4_DA2 (Bit 0)                                     */
#define CAN_PELI_DATA4_DA2_DATA4_DA2_Msk  (0xffUL)                  /*!< DATA4_DA2 (Bitfield-Mask: 0xff)                       */
/* =======================================================  DATA5_DA3  ======================================================= */
#define CAN_PELI_DATA5_DA3_DATA5_DA3_Pos  (0UL)                     /*!< DATA5_DA3 (Bit 0)                                     */
#define CAN_PELI_DATA5_DA3_DATA5_DA3_Msk  (0xffUL)                  /*!< DATA5_DA3 (Bitfield-Mask: 0xff)                       */
/* =======================================================  DATA6_DA4  ======================================================= */
#define CAN_PELI_DATA6_DA4_DATA6_DA4_Pos  (0UL)                     /*!< DATA6_DA4 (Bit 0)                                     */
#define CAN_PELI_DATA6_DA4_DATA6_DA4_Msk  (0xffUL)                  /*!< DATA6_DA4 (Bitfield-Mask: 0xff)                       */
/* =======================================================  DATA7_DA5  ======================================================= */
#define CAN_PELI_DATA7_DA5_DATA7_DA5_Pos  (0UL)                     /*!< DATA7_DA5 (Bit 0)                                     */
#define CAN_PELI_DATA7_DA5_DATA7_DA5_Msk  (0xffUL)                  /*!< DATA7_DA5 (Bitfield-Mask: 0xff)                       */
/* =======================================================  DATA8_DA6  ======================================================= */
#define CAN_PELI_DATA8_DA6_DATA8_DA6_Pos  (0UL)                     /*!< DATA8_DA6 (Bit 0)                                     */
#define CAN_PELI_DATA8_DA6_DATA8_DA6_Msk  (0xffUL)                  /*!< DATA8_DA6 (Bitfield-Mask: 0xff)                       */
/* ========================================================  RES_DA7  ======================================================== */
#define CAN_PELI_RES_DA7_RES_DA7_Pos      (0UL)                     /*!< RES_DA7 (Bit 0)                                       */
#define CAN_PELI_RES_DA7_RES_DA7_Msk      (0xffUL)                  /*!< RES_DA7 (Bitfield-Mask: 0xff)                         */
/* ========================================================  RES_DA8  ======================================================== */
#define CAN_PELI_RES_DA8_RES_DA8_Pos      (0UL)                     /*!< RES_DA8 (Bit 0)                                       */
#define CAN_PELI_RES_DA8_RES_DA8_Msk      (0xffUL)                  /*!< RES_DA8 (Bitfield-Mask: 0xff)                         */
/* ==========================================================  RMC  ========================================================== */
#define CAN_PELI_RMC_RMC_Pos              (0UL)                     /*!< RMC (Bit 0)                                           */
#define CAN_PELI_RMC_RMC_Msk              (0x7fUL)                  /*!< RMC (Bitfield-Mask: 0x7f)                             */
/* ========================================================  EX_CAN  ========================================================= */
#define CAN_PELI_EX_CAN_EX_CAN_Pos        (7UL)                     /*!< EX_CAN (Bit 7)                                        */
#define CAN_PELI_EX_CAN_EX_CAN_Msk        (0x80UL)                  /*!< EX_CAN (Bitfield-Mask: 0x01)                          */



/** @} */ /* End of group PosMask_peripherals */


/* define marco USE_STDPERIPH_DRIVER */
#if !defined  USE_STDPERIPH_DRIVER
#define USE_STDPERIPH_DRIVER
#endif 
#ifdef USE_STDPERIPH_DRIVER
#include "dpm32m0xx_libopt.h"
#endif /* USE_STDPERIPH_DRIVER */



#ifdef __cplusplus
}
#endif

#endif /* DPM32M08X_H */


/** @} */ /* End of group dpm32m08X */

/** @} */ /* End of group DP Ltd. */
